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11#include <common.h>
12#include <pci.h>
13#include <asm/immap.h>
14#include <asm/io.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18int checkboard(void)
19{
20 puts("Board: ");
21 puts("Freescale M54455 EVB\n");
22 return 0;
23};
24
25phys_size_t initdram(int board_type)
26{
27 u32 dramsize;
28#ifdef CONFIG_CF_SBF
29
30
31
32
33 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
34#else
35 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
36 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
37 u32 i;
38
39 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
40
41 for (i = 0x13; i < 0x20; i++) {
42 if (dramsize == (1 << i))
43 break;
44 }
45 i--;
46
47 out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
48
49 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
50 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
51
52 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
53 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
54
55
56 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
57
58
59 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
60 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
61
62 udelay(500);
63
64
65 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
66
67
68 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
69 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
70
71 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
72
73 out_be32(&sdram->sdcr,
74 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
75
76 udelay(100);
77#endif
78 return (dramsize << 1);
79};
80
81int testdram(void)
82{
83
84 printf("DRAM test not implemented!\n");
85
86 return (0);
87}
88
89#if defined(CONFIG_CMD_IDE)
90#include <ata.h>
91
92int ide_preinit(void)
93{
94 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
95 u32 tmp;
96
97 tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
98 setbits_8(&gpio->par_fec, tmp);
99 tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
100 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
101 setbits_be16(&gpio->par_feci2c, tmp);
102
103 setbits_be16(&gpio->par_ata,
104 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
105 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
106 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
107 GPIO_PAR_ATA_IORDY_IORDY);
108 setbits_be16(&gpio->par_pci,
109 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
110
111 return (0);
112}
113
114void ide_set_reset(int idereset)
115{
116 atac_t *ata = (atac_t *) MMAP_ATA;
117 long period;
118
119 int piotms[5][9] = {
120 {70, 165, 60, 30, 50, 5, 20, 0, 35},
121 {50, 125, 45, 20, 35, 5, 15, 0, 35},
122 {30, 100, 30, 15, 20, 5, 10, 0, 35},
123 {30, 80, 30, 10, 20, 5, 10, 0, 35},
124 {25, 70, 20, 10, 20, 5, 10, 0, 35}
125 };
126
127 if (idereset) {
128
129 out_8(&ata->cr, 0);
130 udelay(10000);
131 } else {
132#define CALC_TIMING(t) (t + period - 1) / period
133 period = 1000000000 / gd->bus_clk;
134
135
136 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
137 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
138 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
139 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
140 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
141 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
142 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
143
144
145 out_8(&ata->cr, 0x40);
146 udelay(200000);
147
148 setbits_8(&ata->cr, 0x01);
149 }
150}
151#endif
152
153#if defined(CONFIG_PCI)
154
155
156
157static struct pci_controller hose;
158extern void pci_mcf5445x_init(struct pci_controller *hose);
159
160void pci_init_board(void)
161{
162 pci_mcf5445x_init(&hose);
163}
164#endif
165
166#if defined(CONFIG_FLASH_CFI_LEGACY)
167#include <flash.h>
168ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
169{
170 int sect[] = CONFIG_SYS_ATMEL_SECT;
171 int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
172 int i, j, k;
173
174 if (base != CONFIG_SYS_ATMEL_BASE)
175 return 0;
176
177 info->flash_id = 0x01000000;
178 info->portwidth = 1;
179 info->chipwidth = 1;
180 info->buffer_size = 1;
181 info->erase_blk_tout = 16384;
182 info->write_tout = 2;
183 info->buffer_write_tout = 5;
184 info->vendor = 0xFFF0;
185 info->cmd_reset = 0x00F0;
186 info->interface = FLASH_CFI_X8;
187 info->legacy_unlock = 0;
188 info->manufacturer_id = (u16) ATM_MANUFACT;
189 info->device_id = ATM_ID_LV040;
190 info->device_id2 = 0;
191
192 info->ext_addr = 0;
193 info->cfi_version = 0x3133;
194 info->cfi_offset = 0x0000;
195 info->addr_unlock1 = 0x00000555;
196 info->addr_unlock2 = 0x000002AA;
197 info->name = "CFI conformant";
198
199 info->size = 0;
200 info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
201 info->start[0] = base;
202 for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
203 info->size += sect[i] * sectsz[i];
204
205 for (j = 0; j < sect[i]; j++, k++) {
206 info->start[k + 1] = info->start[k] + sectsz[i];
207 info->protect[k] = 0;
208 }
209 }
210
211 return 1;
212}
213#endif
214
