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7#include <common.h>
8#include <command.h>
9#include <i2c.h>
10#include <netdev.h>
11#include <linux/compiler.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
17#include <asm/fsl_portals.h>
18#include <asm/fsl_liodn.h>
19#include <fm_eth.h>
20#include "t102xrdb.h"
21#ifdef CONFIG_T1024RDB
22#include "cpld.h"
23#elif defined(CONFIG_T1023RDB)
24#include <i2c.h>
25#include <mmc.h>
26#endif
27#include "../common/sleep.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#ifdef CONFIG_T1023RDB
32enum {
33 GPIO1_SD_SEL = 0x00020000,
34 GPIO1_EMMC_SEL,
35 GPIO3_GET_VERSION,
36 GPIO3_BRD_VER_MASK = 0x0c000000,
37 GPIO3_OFFSET = 0x2000,
38 I2C_GET_BANK,
39 I2C_SET_BANK0,
40 I2C_SET_BANK4,
41};
42#endif
43
44int checkboard(void)
45{
46 struct cpu_type *cpu = gd->arch.cpu;
47 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
48 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 u32 srds_s1;
50
51 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
52 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
53
54 printf("Board: %sRDB, ", cpu->name);
55#if defined(CONFIG_T1024RDB)
56 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
57 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
58#elif defined(CONFIG_T1023RDB)
59 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
60#endif
61 printf("boot from ");
62
63#ifdef CONFIG_SDCARD
64 puts("SD/MMC\n");
65#elif CONFIG_SPIFLASH
66 puts("SPI\n");
67#elif defined(CONFIG_T1024RDB)
68 u8 reg;
69
70 reg = CPLD_READ(flash_csr);
71
72 if (reg & CPLD_BOOT_SEL) {
73 puts("NAND\n");
74 } else {
75 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
76 printf("NOR vBank%d\n", reg);
77 }
78#elif defined(CONFIG_T1023RDB)
79#ifdef CONFIG_NAND
80 puts("NAND\n");
81#else
82 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
83#endif
84#endif
85
86 puts("SERDES Reference Clocks:\n");
87 if (srds_s1 == 0x95)
88 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
89 else
90 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
91
92 return 0;
93}
94
95#ifdef CONFIG_T1024RDB
96static void board_mux_lane(void)
97{
98 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
99 u32 srds_prtcl_s1;
100 u8 reg = CPLD_READ(misc_ctl_status);
101
102 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
103 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
104 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
105
106 if (srds_prtcl_s1 == 0x95) {
107
108 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
109 } else {
110
111 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
112 }
113 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
114}
115#endif
116
117int board_early_init_f(void)
118{
119#if defined(CONFIG_DEEP_SLEEP)
120 if (is_warm_boot())
121 fsl_dp_disable_console();
122#endif
123
124 return 0;
125}
126
127int board_early_init_r(void)
128{
129#ifdef CONFIG_SYS_FLASH_BASE
130 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
131 int flash_esel = find_tlb_idx((void *)flashbase, 1);
132
133
134
135
136
137
138 flush_dcache();
139 invalidate_icache();
140 if (flash_esel == -1) {
141
142 puts("Error: Could not find TLB for FLASH BASE\n");
143 flash_esel = 2;
144 } else {
145
146 disable_tlb(flash_esel);
147 }
148
149 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
150 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
151 0, flash_esel, BOOKE_PAGESZ_256M, 1);
152#endif
153
154 set_liodns();
155#ifdef CONFIG_SYS_DPAA_QBMAN
156 setup_portals();
157#endif
158#ifdef CONFIG_T1024RDB
159 board_mux_lane();
160#endif
161
162 return 0;
163}
164
165unsigned long get_board_sys_clk(void)
166{
167 return CONFIG_SYS_CLK_FREQ;
168}
169
170unsigned long get_board_ddr_clk(void)
171{
172 return CONFIG_DDR_CLK_FREQ;
173}
174
175int misc_init_r(void)
176{
177 return 0;
178}
179
180int ft_board_setup(void *blob, bd_t *bd)
181{
182 phys_addr_t base;
183 phys_size_t size;
184
185 ft_cpu_setup(blob, bd);
186
187 base = getenv_bootm_low();
188 size = getenv_bootm_size();
189
190 fdt_fixup_memory(blob, (u64)base, (u64)size);
191
192#ifdef CONFIG_PCI
193 pci_of_setup(blob, bd);
194#endif
195
196 fdt_fixup_liodn(blob);
197 fdt_fixup_dr_usb(blob, bd);
198
199#ifdef CONFIG_SYS_DPAA_FMAN
200 fdt_fixup_fman_ethernet(blob);
201 fdt_fixup_board_enet(blob);
202#endif
203
204#ifdef CONFIG_T1023RDB
205 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
206 fdt_enable_nor(blob);
207#endif
208
209 return 0;
210}
211
212#ifdef CONFIG_T1023RDB
213
214static void fdt_enable_nor(void *blob)
215{
216 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
217
218 if (nodeoff >= 0)
219 fdt_status_okay(blob, nodeoff);
220 else
221 printf("WARNING unable to set status for NOR\n");
222}
223
224int board_mmc_getcd(struct mmc *mmc)
225{
226 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
227 u32 val = in_be32(&pgpio->gpdat);
228
229
230 val &= GPIO1_SD_SEL;
231
232 return val ? -1 : 1;
233}
234
235int board_mmc_getwp(struct mmc *mmc)
236{
237 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
238 u32 val = in_be32(&pgpio->gpdat);
239
240 val &= GPIO1_SD_SEL;
241
242 return val ? -1 : 0;
243}
244
245static u32 t1023rdb_ctrl(u32 ctrl_type)
246{
247 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
248 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
249 u32 val, orig_bus = i2c_get_bus_num();
250 u8 tmp;
251
252 switch (ctrl_type) {
253 case GPIO1_SD_SEL:
254 val = in_be32(&pgpio->gpdat);
255 val |= GPIO1_SD_SEL;
256 out_be32(&pgpio->gpdat, val);
257 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
258 break;
259 case GPIO1_EMMC_SEL:
260 val = in_be32(&pgpio->gpdat);
261 val &= ~GPIO1_SD_SEL;
262 out_be32(&pgpio->gpdat, val);
263 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
264 break;
265 case GPIO3_GET_VERSION:
266 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
267 + GPIO3_OFFSET);
268 val = in_be32(&pgpio->gpdat);
269 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
270 if (val == 0x3)
271 val = 0;
272 return val;
273 case I2C_GET_BANK:
274 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
275 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
276 tmp &= 0x7;
277 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
278 i2c_set_bus_num(orig_bus);
279 return tmp;
280 case I2C_SET_BANK0:
281 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
282 tmp = 0x0;
283 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
284 tmp = 0xf8;
285 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
286
287 out_be32(&gur->rstcr, 0x2);
288 break;
289 case I2C_SET_BANK4:
290 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
291 tmp = 0x1;
292 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
293 tmp = 0xf8;
294 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
295 out_be32(&gur->rstcr, 0x2);
296 break;
297 default:
298 break;
299 }
300 return 0;
301}
302
303static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
304 char * const argv[])
305{
306 if (argc < 2)
307 return CMD_RET_USAGE;
308 if (!strcmp(argv[1], "bank0"))
309 t1023rdb_ctrl(I2C_SET_BANK0);
310 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
311 t1023rdb_ctrl(I2C_SET_BANK4);
312 else if (!strcmp(argv[1], "sd"))
313 t1023rdb_ctrl(GPIO1_SD_SEL);
314 else if (!strcmp(argv[1], "emmc"))
315 t1023rdb_ctrl(GPIO1_EMMC_SEL);
316 else
317 return CMD_RET_USAGE;
318 return 0;
319}
320
321U_BOOT_CMD(
322 switch, 2, 0, switch_cmd,
323 "for bank0/bank4/sd/emmc switch control in runtime",
324 "command (e.g. switch bank4)"
325);
326#endif
327
