LXR uboot/board/renesas/ap325rxa/ap325rxa.c

   1/*
   2 * Copyright (C) 2008 Renesas Solutions Corp.
   3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <netdev.h>
  10#include <asm/io.h>
  11#include <asm/processor.h>
  12
  13DECLARE_GLOBAL_DATA_PTR;
  14
  15/* PRI control register */
  16#define PRPRICR5        0xFF800048 /* LMB */
  17#define PRPRICR5_D      0x2a
  18
  19/* FPGA control */
  20#define FPGA_NAND_CTL   0xB410020C
  21#define FPGA_NAND_RST   0x0008
  22#define FPGA_NAND_INIT  0x0000
  23#define FPGA_NAND_RST_WAIT      10000
  24
  25/* I/O port data */
  26#define PACR_D  0x0000
  27#define PBCR_D  0x0000
  28#define PCCR_D  0x1000
  29#define PDCR_D  0x0000
  30#define PECR_D  0x0410
  31#define PFCR_D  0xffff
  32#define PGCR_D  0x0000
  33#define PHCR_D  0x5011
  34#define PJCR_D  0x4400
  35#define PKCR_D  0x7c00
  36#define PLCR_D  0x0000
  37#define PMCR_D  0x0000
  38#define PNCR_D  0x0000
  39#define PQCR_D  0x0000
  40#define PRCR_D  0x0000
  41#define PSCR_D  0x0000
  42#define PTCR_D  0x0010
  43#define PUCR_D  0x0fff
  44#define PVCR_D  0xffff
  45#define PWCR_D  0x0000
  46#define PXCR_D  0x7500
  47#define PYCR_D  0x0000
  48#define PZCR_D  0x5540
  49
  50/* Pin Function Controler data */
  51#define PSELA_D 0x1410
  52#define PSELB_D 0x0140
  53#define PSELC_D 0x0000
  54#define PSELD_D 0x0400
  55
  56/* I/O Buffer Hi-Z data */
  57#define HIZCRA_D        0x0000
  58#define HIZCRB_D        0x1000
  59#define HIZCRC_D        0x0000
  60#define HIZCRD_D        0x0000
  61
  62/* Module select reg data */
  63#define MSELCRA_D       0x0014
  64#define MSELCRB_D       0x0018
  65
  66/* Module Stop reg Data */
  67#define MSTPCR2_D       0xFFD9F280
  68
  69/* CPLD loader */
  70extern void init_cpld(void);
  71
  72int checkboard(void)
  73{
  74        puts("BOARD: AP325RXA\n");
  75        return 0;
  76}
  77
  78int board_init(void)
  79{
  80        /* Pin Function Controler Init */
  81        outw(PSELA_D, PSELA);
  82        outw(PSELB_D, PSELB);
  83        outw(PSELC_D, PSELC);
  84        outw(PSELD_D, PSELD);
  85
  86        /* I/O Buffer Hi-Z Init */
  87        outw(HIZCRA_D, HIZCRA);
  88        outw(HIZCRB_D, HIZCRB);
  89        outw(HIZCRC_D, HIZCRC);
  90        outw(HIZCRD_D, HIZCRD);
  91
  92        /* Module select reg Init */
  93        outw(MSELCRA_D, MSELCRA);
  94        outw(MSELCRB_D, MSELCRB);
  95
  96        /* Module Stop reg Init */
  97        outl(MSTPCR2_D, MSTPCR2);
  98
  99        /* I/O ports */
 100        outw(PACR_D, PACR);
 101        outw(PBCR_D, PBCR);
 102        outw(PCCR_D, PCCR);
 103        outw(PDCR_D, PDCR);
 104        outw(PECR_D, PECR);
 105        outw(PFCR_D, PFCR);
 106        outw(PGCR_D, PGCR);
 107        outw(PHCR_D, PHCR);
 108        outw(PJCR_D, PJCR);
 109        outw(PKCR_D, PKCR);
 110        outw(PLCR_D, PLCR);
 111        outw(PMCR_D, PMCR);
 112        outw(PNCR_D, PNCR);
 113        outw(PQCR_D, PQCR);
 114        outw(PRCR_D, PRCR);
 115        outw(PSCR_D, PSCR);
 116        outw(PTCR_D, PTCR);
 117        outw(PUCR_D, PUCR);
 118        outw(PVCR_D, PVCR);
 119        outw(PWCR_D, PWCR);
 120        outw(PXCR_D, PXCR);
 121        outw(PYCR_D, PYCR);
 122        outw(PZCR_D, PZCR);
 123
 124        /* PRI control register Init */
 125        outl(PRPRICR5_D, PRPRICR5);
 126
 127        /* cpld init */
 128        init_cpld();
 129
 130        return 0;
 131}
 132
 133int dram_init(void)
 134{
 135        gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 136        gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 137        printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 138        return 0;
 139}
 140
 141void led_set_state(unsigned short value)
 142{
 143}
 144
 145void ide_set_reset(int idereset)
 146{
 147        outw(FPGA_NAND_RST, FPGA_NAND_CTL);     /* NAND RESET */
 148        udelay(FPGA_NAND_RST_WAIT);
 149        outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
 150}
 151
 152int board_eth_init(bd_t *bis)
 153{
 154        int rc = 0;
 155#ifdef CONFIG_SMC911X
 156        rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 157#endif
 158        return rc;
 159}
 160