1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#include <common.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/imx-regs.h>
20#include <asm/errno.h>
21#include <asm/imx-common/mxc_i2c.h>
22#include <asm/io.h>
23#include <i2c.h>
24#include <watchdog.h>
25#include <dm.h>
26#include <fdtdec.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define I2C_QUIRK_FLAG (1 << 0)
31
32#define IMX_I2C_REGSHIFT 2
33#define VF610_I2C_REGSHIFT 0
34
35#define IADR 0
36#define IFDR 1
37#define I2CR 2
38#define I2SR 3
39#define I2DR 4
40
41#define I2CR_IIEN (1 << 6)
42#define I2CR_MSTA (1 << 5)
43#define I2CR_MTX (1 << 4)
44#define I2CR_TX_NO_AK (1 << 3)
45#define I2CR_RSTA (1 << 2)
46
47#define I2SR_ICF (1 << 7)
48#define I2SR_IBB (1 << 5)
49#define I2SR_IAL (1 << 4)
50#define I2SR_IIF (1 << 1)
51#define I2SR_RX_NO_AK (1 << 0)
52
53#ifdef I2C_QUIRK_REG
54#define I2CR_IEN (0 << 7)
55#define I2CR_IDIS (1 << 7)
56#define I2SR_IIF_CLEAR (1 << 1)
57#else
58#define I2CR_IEN (1 << 7)
59#define I2CR_IDIS (0 << 7)
60#define I2SR_IIF_CLEAR (0 << 1)
61#endif
62
63#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
64#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
65#endif
66
67#ifdef I2C_QUIRK_REG
68static u16 i2c_clk_div[60][2] = {
69 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
70 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
71 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
72 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
73 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
74 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
75 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
76 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
77 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
78 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
79 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
80 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
81 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
82 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
83 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
84};
85#else
86static u16 i2c_clk_div[50][2] = {
87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
99 { 3072, 0x1E }, { 3840, 0x1F }
100};
101#endif
102
103#ifndef CONFIG_SYS_MXC_I2C1_SPEED
104#define CONFIG_SYS_MXC_I2C1_SPEED 100000
105#endif
106#ifndef CONFIG_SYS_MXC_I2C2_SPEED
107#define CONFIG_SYS_MXC_I2C2_SPEED 100000
108#endif
109#ifndef CONFIG_SYS_MXC_I2C3_SPEED
110#define CONFIG_SYS_MXC_I2C3_SPEED 100000
111#endif
112#ifndef CONFIG_SYS_MXC_I2C4_SPEED
113#define CONFIG_SYS_MXC_I2C4_SPEED 100000
114#endif
115
116#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
117#define CONFIG_SYS_MXC_I2C1_SLAVE 0
118#endif
119#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
120#define CONFIG_SYS_MXC_I2C2_SLAVE 0
121#endif
122#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
123#define CONFIG_SYS_MXC_I2C3_SLAVE 0
124#endif
125#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
126#define CONFIG_SYS_MXC_I2C4_SLAVE 0
127#endif
128
129
130
131
132static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
133{
134 unsigned int i2c_clk_rate;
135 unsigned int div;
136 u8 clk_div;
137
138#if defined(CONFIG_MX31)
139 struct clock_control_regs *sc_regs =
140 (struct clock_control_regs *)CCM_BASE;
141
142
143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
144 &sc_regs->cgr0);
145#endif
146
147
148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
149 div = (i2c_clk_rate + rate - 1) / rate;
150 if (div < i2c_clk_div[0][0])
151 clk_div = 0;
152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
154 else
155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
156 ;
157
158
159 return clk_div;
160}
161
162
163
164
165static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
166{
167 ulong base = i2c_bus->base;
168 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
169 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
170 u8 idx = i2c_clk_div[clk_idx][1];
171 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
172
173 if (!base)
174 return -ENODEV;
175
176
177 writeb(idx, base + (IFDR << reg_shift));
178
179
180 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
181 writeb(0, base + (I2SR << reg_shift));
182 return 0;
183}
184
185#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
186#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
187#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
188
189static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
190{
191 unsigned sr;
192 ulong elapsed;
193 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
194 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
195 ulong base = i2c_bus->base;
196 ulong start_time = get_timer(0);
197 for (;;) {
198 sr = readb(base + (I2SR << reg_shift));
199 if (sr & I2SR_IAL) {
200 if (quirk)
201 writeb(sr | I2SR_IAL, base +
202 (I2SR << reg_shift));
203 else
204 writeb(sr & ~I2SR_IAL, base +
205 (I2SR << reg_shift));
206 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
207 __func__, sr, readb(base + (I2CR << reg_shift)),
208 state);
209 return -ERESTART;
210 }
211 if ((sr & (state >> 8)) == (unsigned char)state)
212 return sr;
213 WATCHDOG_RESET();
214 elapsed = get_timer(start_time);
215 if (elapsed > (CONFIG_SYS_HZ / 10))
216 break;
217 }
218 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
219 sr, readb(base + (I2CR << reg_shift)), state);
220 return -ETIMEDOUT;
221}
222
223static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
224{
225 int ret;
226 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
227 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
228 ulong base = i2c_bus->base;
229
230 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
231 writeb(byte, base + (I2DR << reg_shift));
232
233 ret = wait_for_sr_state(i2c_bus, ST_IIF);
234 if (ret < 0)
235 return ret;
236 if (ret & I2SR_RX_NO_AK)
237 return -ENODEV;
238 return 0;
239}
240
241
242
243
244void __i2c_force_reset_slave(void)
245{
246}
247void i2c_force_reset_slave(void)
248 __attribute__((weak, alias("__i2c_force_reset_slave")));
249
250
251
252
253static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
254{
255 int ret;
256 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
257 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
258 ulong base = i2c_bus->base;
259 unsigned int temp = readb(base + (I2CR << reg_shift));
260
261 temp &= ~(I2CR_MSTA | I2CR_MTX);
262 writeb(temp, base + (I2CR << reg_shift));
263 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
264 if (ret < 0)
265 printf("%s:trigger stop failed\n", __func__);
266}
267
268
269
270
271
272static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
273 u32 addr, int alen)
274{
275 unsigned int temp;
276 int ret;
277 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
278 ulong base = i2c_bus->base;
279 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
280
281
282 i2c_force_reset_slave();
283
284
285 if (quirk)
286 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
287 else
288 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
289
290 if (ret) {
291 writeb(I2CR_IEN, base + (I2CR << reg_shift));
292
293 udelay(50);
294 }
295
296 if (readb(base + (IADR << reg_shift)) == (chip << 1))
297 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
298 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
299 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
300 if (ret < 0)
301 return ret;
302
303
304 temp = readb(base + (I2CR << reg_shift));
305 temp |= I2CR_MSTA;
306 writeb(temp, base + (I2CR << reg_shift));
307
308 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
309 if (ret < 0)
310 return ret;
311
312 temp |= I2CR_MTX | I2CR_TX_NO_AK;
313 writeb(temp, base + (I2CR << reg_shift));
314
315
316 ret = tx_byte(i2c_bus, chip << 1);
317 if (ret < 0)
318 return ret;
319
320 while (alen--) {
321 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
322 if (ret < 0)
323 return ret;
324 }
325 return 0;
326}
327
328#ifndef CONFIG_DM_I2C
329int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
330{
331 if (i2c_bus && i2c_bus->idle_bus_fn)
332 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
333 return 0;
334}
335#else
336
337
338
339
340
341int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
342{
343 return 0;
344}
345
346int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
347 __attribute__((weak, alias("__i2c_idle_bus")));
348#endif
349
350static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
351 u32 addr, int alen)
352{
353 int retry;
354 int ret;
355 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
356 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
357
358 if (!i2c_bus->base)
359 return -ENODEV;
360
361 for (retry = 0; retry < 3; retry++) {
362 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
363 if (ret >= 0)
364 return 0;
365 i2c_imx_stop(i2c_bus);
366 if (ret == -ENODEV)
367 return ret;
368
369 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
370 retry);
371 if (ret != -ERESTART)
372
373 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
374 udelay(100);
375 if (i2c_idle_bus(i2c_bus) < 0)
376 break;
377 }
378 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
379 return ret;
380}
381
382
383static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
384 int len)
385{
386 int i, ret = 0;
387
388 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
389 debug("write_data: ");
390
391 for (i = 0; i < len; ++i)
392 debug(" 0x%02x", buf[i]);
393 debug("\n");
394
395 for (i = 0; i < len; i++) {
396 ret = tx_byte(i2c_bus, buf[i]);
397 if (ret < 0) {
398 debug("i2c_write_data(): rc=%d\n", ret);
399 break;
400 }
401 }
402
403 return ret;
404}
405
406static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
407 int len)
408{
409 int ret;
410 unsigned int temp;
411 int i;
412 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
413 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
414 ulong base = i2c_bus->base;
415
416 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
417
418
419 temp = readb(base + (I2CR << reg_shift));
420 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
421 if (len == 1)
422 temp |= I2CR_TX_NO_AK;
423 writeb(temp, base + (I2CR << reg_shift));
424 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
425
426 readb(base + (I2DR << reg_shift));
427
428
429 for (i = 0; i < len; i++) {
430 ret = wait_for_sr_state(i2c_bus, ST_IIF);
431 if (ret < 0) {
432 debug("i2c_read_data(): ret=%d\n", ret);
433 i2c_imx_stop(i2c_bus);
434 return ret;
435 }
436
437
438
439
440
441 if (i == (len - 1)) {
442 i2c_imx_stop(i2c_bus);
443 } else if (i == (len - 2)) {
444 temp = readb(base + (I2CR << reg_shift));
445 temp |= I2CR_TX_NO_AK;
446 writeb(temp, base + (I2CR << reg_shift));
447 }
448 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
449 buf[i] = readb(base + (I2DR << reg_shift));
450 }
451
452
453 for (ret = 0; ret < len; ++ret)
454 debug(" 0x%02x", buf[ret]);
455 debug("\n");
456
457 i2c_imx_stop(i2c_bus);
458 return 0;
459}
460
461#ifndef CONFIG_DM_I2C
462
463
464
465static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
466 int alen, u8 *buf, int len)
467{
468 int ret = 0;
469 u32 temp;
470 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
471 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
472 ulong base = i2c_bus->base;
473
474 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
475 if (ret < 0)
476 return ret;
477
478 temp = readb(base + (I2CR << reg_shift));
479 temp |= I2CR_RSTA;
480 writeb(temp, base + (I2CR << reg_shift));
481
482 ret = tx_byte(i2c_bus, (chip << 1) | 1);
483 if (ret < 0) {
484 i2c_imx_stop(i2c_bus);
485 return ret;
486 }
487
488 ret = i2c_read_data(i2c_bus, chip, buf, len);
489
490 i2c_imx_stop(i2c_bus);
491 return ret;
492}
493
494
495
496
497static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
498 int alen, const u8 *buf, int len)
499{
500 int ret = 0;
501
502 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
503 if (ret < 0)
504 return ret;
505
506 ret = i2c_write_data(i2c_bus, chip, buf, len);
507
508 i2c_imx_stop(i2c_bus);
509
510 return ret;
511}
512
513#if !defined(I2C2_BASE_ADDR)
514#define I2C2_BASE_ADDR 0
515#endif
516
517#if !defined(I2C3_BASE_ADDR)
518#define I2C3_BASE_ADDR 0
519#endif
520
521#if !defined(I2C4_BASE_ADDR)
522#define I2C4_BASE_ADDR 0
523#endif
524
525static struct mxc_i2c_bus mxc_i2c_buses[] = {
526#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
527 defined(CONFIG_FSL_LAYERSCAPE)
528 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
529 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
530 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
531 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
532#else
533 { 0, I2C1_BASE_ADDR, 0 },
534 { 1, I2C2_BASE_ADDR, 0 },
535 { 2, I2C3_BASE_ADDR, 0 },
536 { 3, I2C4_BASE_ADDR, 0 },
537#endif
538};
539
540struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
541{
542 return &mxc_i2c_buses[adap->hwadapnr];
543}
544
545static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
546 uint addr, int alen, uint8_t *buffer,
547 int len)
548{
549 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
550}
551
552static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
553 uint addr, int alen, uint8_t *buffer,
554 int len)
555{
556 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
557}
558
559
560
561
562static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
563{
564 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
565}
566
567int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
568{
569 return 1;
570}
571int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
572 __attribute__((weak, alias("__enable_i2c_clk")));
573
574void bus_i2c_init(int index, int speed, int unused,
575 int (*idle_bus_fn)(void *p), void *idle_bus_data)
576{
577 int ret;
578
579 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
580 debug("Error i2c index\n");
581 return;
582 }
583
584
585
586
587
588
589
590 if (idle_bus_fn)
591 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
592 if (idle_bus_data)
593 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
594
595 ret = enable_i2c_clk(1, index);
596 if (ret < 0) {
597 debug("I2C-%d clk fail to enable.\n", index);
598 return;
599 }
600
601 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
602}
603
604
605
606
607static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
608{
609 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
610}
611
612
613
614
615static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
616{
617 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
618}
619
620
621
622
623#ifdef CONFIG_SYS_I2C_MXC_I2C1
624U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
625 mxc_i2c_read, mxc_i2c_write,
626 mxc_i2c_set_bus_speed,
627 CONFIG_SYS_MXC_I2C1_SPEED,
628 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
629#endif
630
631#ifdef CONFIG_SYS_I2C_MXC_I2C2
632U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
633 mxc_i2c_read, mxc_i2c_write,
634 mxc_i2c_set_bus_speed,
635 CONFIG_SYS_MXC_I2C2_SPEED,
636 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
637#endif
638
639#ifdef CONFIG_SYS_I2C_MXC_I2C3
640U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
641 mxc_i2c_read, mxc_i2c_write,
642 mxc_i2c_set_bus_speed,
643 CONFIG_SYS_MXC_I2C3_SPEED,
644 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
645#endif
646
647#ifdef CONFIG_SYS_I2C_MXC_I2C4
648U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
649 mxc_i2c_read, mxc_i2c_write,
650 mxc_i2c_set_bus_speed,
651 CONFIG_SYS_MXC_I2C4_SPEED,
652 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
653#endif
654
655#else
656
657static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
658{
659 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
660
661 return bus_i2c_set_bus_speed(i2c_bus, speed);
662}
663
664static int mxc_i2c_probe(struct udevice *bus)
665{
666 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
667 fdt_addr_t addr;
668 int ret;
669
670 i2c_bus->driver_data = dev_get_driver_data(bus);
671
672 addr = dev_get_addr(bus);
673 if (addr == FDT_ADDR_T_NONE)
674 return -ENODEV;
675
676 i2c_bus->base = addr;
677 i2c_bus->index = bus->seq;
678
679
680 ret = enable_i2c_clk(1, bus->seq);
681 if (ret < 0)
682 return ret;
683
684 ret = i2c_idle_bus(i2c_bus);
685 if (ret < 0) {
686
687 enable_i2c_clk(0, bus->seq);
688 return ret;
689 }
690
691
692
693
694
695
696 debug("i2c : controller bus %d at %lu , speed %d: ",
697 bus->seq, i2c_bus->base,
698 i2c_bus->speed);
699
700 return 0;
701}
702
703static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
704 u32 chip_flags)
705{
706 int ret;
707 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
708
709 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
710 if (ret < 0) {
711 debug("%s failed, ret = %d\n", __func__, ret);
712 return ret;
713 }
714
715 i2c_imx_stop(i2c_bus);
716
717 return 0;
718}
719
720static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
721{
722 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
723 int ret = 0;
724 ulong base = i2c_bus->base;
725 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
726 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
727
728
729
730
731
732
733 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
734 if (ret < 0) {
735 debug("i2c_init_transfer error: %d\n", ret);
736 return ret;
737 }
738
739 for (; nmsgs > 0; nmsgs--, msg++) {
740 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
741 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
742 if (msg->flags & I2C_M_RD)
743 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
744 msg->len);
745 else {
746 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
747 msg->len);
748 if (ret)
749 break;
750 if (next_is_read) {
751
752 ret = readb(base + (I2CR << reg_shift));
753 ret |= I2CR_RSTA;
754 writeb(ret, base + (I2CR << reg_shift));
755
756 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
757 if (ret < 0) {
758 i2c_imx_stop(i2c_bus);
759 break;
760 }
761 }
762 }
763 }
764
765 if (ret)
766 debug("i2c_write: error sending\n");
767
768 i2c_imx_stop(i2c_bus);
769
770 return ret;
771}
772
773static const struct dm_i2c_ops mxc_i2c_ops = {
774 .xfer = mxc_i2c_xfer,
775 .probe_chip = mxc_i2c_probe_chip,
776 .set_bus_speed = mxc_i2c_set_bus_speed,
777};
778
779static const struct udevice_id mxc_i2c_ids[] = {
780 { .compatible = "fsl,imx21-i2c", },
781 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
782 {}
783};
784
785U_BOOT_DRIVER(i2c_mxc) = {
786 .name = "i2c_mxc",
787 .id = UCLASS_I2C,
788 .of_match = mxc_i2c_ids,
789 .probe = mxc_i2c_probe,
790 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
791 .ops = &mxc_i2c_ops,
792};
793#endif
794
