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8#include <common.h>
9#include <debug_uart.h>
10#include <dm.h>
11#include <errno.h>
12#include <fdtdec.h>
13#include <watchdog.h>
14#include <asm/io.h>
15#include <linux/compiler.h>
16#include <serial.h>
17#include <asm/arch/clk.h>
18#include <asm/arch/hardware.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#define ZYNQ_UART_SR_TXFULL 0x00000010
23#define ZYNQ_UART_SR_TXACTIVE (1 << 11)
24#define ZYNQ_UART_SR_RXEMPTY 0x00000002
25
26#define ZYNQ_UART_CR_TX_EN 0x00000010
27#define ZYNQ_UART_CR_RX_EN 0x00000004
28#define ZYNQ_UART_CR_TXRST 0x00000002
29#define ZYNQ_UART_CR_RXRST 0x00000001
30
31#define ZYNQ_UART_MR_PARITY_NONE 0x00000020
32
33struct uart_zynq {
34 u32 control;
35 u32 mode;
36 u32 reserved1[4];
37 u32 baud_rate_gen;
38 u32 reserved2[4];
39 u32 channel_sts;
40 u32 tx_rx_fifo;
41 u32 baud_rate_divider;
42};
43
44struct zynq_uart_priv {
45 struct uart_zynq *regs;
46};
47
48
49static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
50 unsigned long clock, unsigned long baud)
51{
52
53 unsigned int calc_bauderror, bdiv, bgen;
54 unsigned long calc_baud = 0;
55
56
57 if (clock < 1000000 && baud > 4800)
58 baud = 4800;
59
60
61
62
63
64
65
66 for (bdiv = 4; bdiv < 255; bdiv++) {
67 bgen = clock / (baud * (bdiv + 1));
68 if (bgen < 2 || bgen > 65535)
69 continue;
70
71 calc_baud = clock / (bgen * (bdiv + 1));
72
73
74
75
76
77 if (baud > calc_baud)
78 calc_bauderror = baud - calc_baud;
79 else
80 calc_bauderror = calc_baud - baud;
81 if (((calc_bauderror * 100) / baud) < 3)
82 break;
83 }
84
85 writel(bdiv, ®s->baud_rate_divider);
86 writel(bgen, ®s->baud_rate_gen);
87}
88
89
90static void _uart_zynq_serial_init(struct uart_zynq *regs)
91{
92
93 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
94 ZYNQ_UART_CR_RXRST, ®s->control);
95 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode);
96}
97
98static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
99{
100 if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
101 return -EAGAIN;
102
103 writel(c, ®s->tx_rx_fifo);
104
105 return 0;
106}
107
108int zynq_serial_setbrg(struct udevice *dev, int baudrate)
109{
110 struct zynq_uart_priv *priv = dev_get_priv(dev);
111 unsigned long clock = get_uart_clk(0);
112
113 _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
114
115 return 0;
116}
117
118static int zynq_serial_probe(struct udevice *dev)
119{
120 struct zynq_uart_priv *priv = dev_get_priv(dev);
121
122 _uart_zynq_serial_init(priv->regs);
123
124 return 0;
125}
126
127static int zynq_serial_getc(struct udevice *dev)
128{
129 struct zynq_uart_priv *priv = dev_get_priv(dev);
130 struct uart_zynq *regs = priv->regs;
131
132 if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
133 return -EAGAIN;
134
135 return readl(®s->tx_rx_fifo);
136}
137
138static int zynq_serial_putc(struct udevice *dev, const char ch)
139{
140 struct zynq_uart_priv *priv = dev_get_priv(dev);
141
142 return _uart_zynq_serial_putc(priv->regs, ch);
143}
144
145static int zynq_serial_pending(struct udevice *dev, bool input)
146{
147 struct zynq_uart_priv *priv = dev_get_priv(dev);
148 struct uart_zynq *regs = priv->regs;
149
150 if (input)
151 return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
152 else
153 return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
154}
155
156static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
157{
158 struct zynq_uart_priv *priv = dev_get_priv(dev);
159 fdt_addr_t addr;
160
161 addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
162 if (addr == FDT_ADDR_T_NONE)
163 return -EINVAL;
164
165 priv->regs = (struct uart_zynq *)addr;
166
167 return 0;
168}
169
170static const struct dm_serial_ops zynq_serial_ops = {
171 .putc = zynq_serial_putc,
172 .pending = zynq_serial_pending,
173 .getc = zynq_serial_getc,
174 .setbrg = zynq_serial_setbrg,
175};
176
177static const struct udevice_id zynq_serial_ids[] = {
178 { .compatible = "xlnx,xuartps" },
179 { .compatible = "cdns,uart-r1p8" },
180 { }
181};
182
183U_BOOT_DRIVER(serial_zynq) = {
184 .name = "serial_zynq",
185 .id = UCLASS_SERIAL,
186 .of_match = zynq_serial_ids,
187 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
188 .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
189 .probe = zynq_serial_probe,
190 .ops = &zynq_serial_ops,
191 .flags = DM_FLAG_PRE_RELOC,
192};
193
194#ifdef CONFIG_DEBUG_UART_ZYNQ
195static inline void _debug_uart_init(void)
196{
197 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
198
199 _uart_zynq_serial_init(regs);
200 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
201 CONFIG_BAUDRATE);
202}
203
204static inline void _debug_uart_putc(int ch)
205{
206 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
207
208 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
209 WATCHDOG_RESET();
210}
211
212DEBUG_UART_FUNCS
213
214#endif
215