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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18
19
20#define CONFIG_405GP 1
21#define CONFIG_CPCI405 1
22#define CONFIG_CPCI405_VER2 1
23#undef CONFIG_CPCI405_6U
24
25#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26#define CONFIG_DISPLAY_BOARDINFO
27
28#define CONFIG_BOARD_EARLY_INIT_F 1
29#define CONFIG_MISC_INIT_R 1
30
31#define CONFIG_SYS_CLK_FREQ 33330000
32
33#define CONFIG_BAUDRATE 9600
34#define CONFIG_BOOTDELAY 3
35
36#undef CONFIG_BOOTARGS
37#undef CONFIG_BOOTCOMMAND
38
39#define CONFIG_PREBOOT
40
41#define CONFIG_LOADS_ECHO 1
42#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
43
44#define CONFIG_PPC4xx_EMAC
45#define CONFIG_MII 1
46#define CONFIG_PHY_ADDR 0
47#define CONFIG_LXT971_NO_SLEEP 1
48#define CONFIG_RESET_PHY_R 1
49
50#undef CONFIG_HAS_ETH1
51
52#define CONFIG_RTC_M48T35A 1
53
54
55
56
57#define CONFIG_BOOTP_SUBNETMASK
58#define CONFIG_BOOTP_GATEWAY
59#define CONFIG_BOOTP_HOSTNAME
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_DNS
62#define CONFIG_BOOTP_DNS2
63#define CONFIG_BOOTP_SEND_HOSTNAME
64
65
66
67
68
69#define CONFIG_CMD_DHCP
70#define CONFIG_CMD_PCI
71#define CONFIG_CMD_IRQ
72#define CONFIG_CMD_IDE
73#define CONFIG_CMD_FAT
74#define CONFIG_CMD_DATE
75#define CONFIG_CMD_I2C
76#define CONFIG_CMD_MII
77#define CONFIG_CMD_PING
78#define CONFIG_CMD_BSP
79#define CONFIG_CMD_EEPROM
80
81#define CONFIG_MAC_PARTITION
82#define CONFIG_DOS_PARTITION
83
84#define CONFIG_SUPPORT_VFAT
85
86#undef CONFIG_WATCHDOG
87
88#define CONFIG_SDRAM_BANK0 1
89
90
91
92
93#undef CONFIG_SYS_LONGHELP
94
95#undef CONFIG_SYS_HUSH_PARSER
96
97#if defined(CONFIG_CMD_KGDB)
98#define CONFIG_SYS_CBSIZE 1024
99#else
100#define CONFIG_SYS_CBSIZE 256
101#endif
102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
103#define CONFIG_SYS_MAXARGS 16
104#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
105
106#define CONFIG_SYS_DEVICE_NULLDEV 1
107
108#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
109
110#define CONFIG_AUTO_COMPLETE 1
111
112#define CONFIG_SYS_MEMTEST_START 0x0400000
113#define CONFIG_SYS_MEMTEST_END 0x0C00000
114
115#define CONFIG_CONS_INDEX 1
116#define CONFIG_SYS_NS16550_SERIAL
117#define CONFIG_SYS_NS16550_REG_SIZE 1
118#define CONFIG_SYS_NS16550_CLK get_serial_clock()
119
120#undef CONFIG_SYS_EXT_SERIAL_CLOCK
121#define CONFIG_SYS_BASE_BAUD 691200
122
123
124#define CONFIG_SYS_BAUDRATE_TABLE \
125 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
126 57600, 115200, 230400, 460800, 921600 }
127
128#define CONFIG_SYS_LOAD_ADDR 0x100000
129#define CONFIG_SYS_EXTBDINFO 1
130
131#define CONFIG_CMDLINE_EDITING
132
133#define CONFIG_LOOPW 1
134
135#define CONFIG_ZERO_BOOTDELAY_CHECK
136
137#define CONFIG_VERSION_VARIABLE 1
138
139#define CONFIG_SYS_RX_ETH_BUFFER 16
140
141
142
143
144
145#define PCI_HOST_ADAPTER 0
146#define PCI_HOST_FORCE 1
147#define PCI_HOST_AUTO 2
148
149#define CONFIG_PCI
150#define CONFIG_PCI_INDIRECT_BRIDGE
151#define CONFIG_PCI_HOST PCI_HOST_AUTO
152#define CONFIG_PCI_PNP
153
154
155#define CONFIG_PCI_SCAN_SHOW
156
157#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
158
159#define CONFIG_PCI_BOOTDELAY 0
160
161#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
162#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
163#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406
164#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
165#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart)
166#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1)
167#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
168#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
169#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
170#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize)
171
172#define CONFIG_PCI_4xx_PTM_OVERWRITE 1
173
174
175
176
177
178#undef CONFIG_IDE_8xx_DIRECT
179#undef CONFIG_IDE_LED
180#define CONFIG_IDE_RESET 1
181
182#define CONFIG_SYS_IDE_MAXBUS 1
183#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
184
185#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
186#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
187
188#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
189#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
190#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
191
192
193
194
195
196
197#define CONFIG_SYS_SDRAM_BASE 0x00000000
198#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
199#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
200#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
201#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
202
203#define CONFIG_PRAM 0
204
205
206
207
208
209
210#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
211
212#define CONFIG_OF_LIBFDT
213#define CONFIG_OF_BOARD_SETUP
214
215
216
217
218#define CONFIG_SYS_MAX_FLASH_BANKS 2
219#define CONFIG_SYS_MAX_FLASH_SECT 256
220
221#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
222#define CONFIG_SYS_FLASH_WRITE_TOUT 500
223
224#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
225#define CONFIG_SYS_FLASH_ADDR0 0x5555
226#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
227
228
229
230
231#define CONFIG_SYS_FLASH_READ0 0x0000
232#define CONFIG_SYS_FLASH_READ1 0x0001
233#define CONFIG_SYS_FLASH_READ2 0x0002
234
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236
237#if 0
238
239
240
241#define CONFIG_ENV_IS_IN_NVRAM 1
242#define CONFIG_ENV_SIZE 0x0ff8
243#define CONFIG_ENV_ADDR \
244 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))
245
246#else
247
248#define CONFIG_ENV_IS_IN_EEPROM 1
249#define CONFIG_ENV_OFFSET 0x000
250#define CONFIG_ENV_SIZE 0x800
251
252#endif
253
254#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
255#define CONFIG_SYS_NVRAM_SIZE (32*1024)
256#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900)
257
258
259
260
261#define CONFIG_SYS_I2C
262#define CONFIG_SYS_I2C_PPC4XX
263#define CONFIG_SYS_I2C_PPC4XX_CH0
264#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
265#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
266
267#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
268#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
269
270#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
271#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
272
273
274#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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276
277
278
279
280
281
282#define FLASH_BASE0_PRELIM 0xFF800000
283#define FLASH_BASE1_PRELIM 0xFFC00000
284
285
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287
288
289
290#define CONFIG_SYS_EBC_PB0AP 0x92015480
291#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
292
293
294#define CONFIG_SYS_EBC_PB1AP 0x92015480
295#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
296
297
298#define CONFIG_SYS_EBC_PB2AP 0x010053C0
299#define CONFIG_SYS_EBC_PB2CR 0xF0018000
300#define CONFIG_SYS_LED_ADDR 0xF0000380
301
302
303#define CONFIG_SYS_EBC_PB3AP 0x010053C0
304#define CONFIG_SYS_EBC_PB3CR 0xF011A000
305
306
307
308#define CONFIG_SYS_EBC_PB4AP 0x01805680
309#define CONFIG_SYS_EBC_PB4CR 0xF0218000
310
311
312#define CONFIG_SYS_EBC_PB5AP 0x04005B80
313#define CONFIG_SYS_EBC_PB5CR 0xF0318000
314
315
316#define CONFIG_SYS_EBC_PB6AP 0x010053C0
317#define CONFIG_SYS_EBC_PB6CR 0xF041A000
318#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
319
320
321
322
323
324#define CONFIG_SYS_FPGA_MODE 0x00
325#define CONFIG_SYS_FPGA_STATUS 0x02
326#define CONFIG_SYS_FPGA_TS 0x04
327#define CONFIG_SYS_FPGA_TS_LOW 0x06
328#define CONFIG_SYS_FPGA_TS_CAP0 0x10
329#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
330#define CONFIG_SYS_FPGA_TS_CAP1 0x14
331#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
332#define CONFIG_SYS_FPGA_TS_CAP2 0x18
333#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
334#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
335#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
336
337
338#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
339#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
340#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004
341#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
342#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
343#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
344
345
346#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
347#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
348#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
349#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
350#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
351
352#define CONFIG_SYS_FPGA_SPARTAN2 1
353#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
354
355
356#define CONFIG_SYS_FPGA_PRG 0x04000000
357#define CONFIG_SYS_FPGA_CLK 0x02000000
358#define CONFIG_SYS_FPGA_DATA 0x01000000
359#define CONFIG_SYS_FPGA_INIT 0x00010000
360#define CONFIG_SYS_FPGA_DONE 0x00008000
361
362
363
364
365#define CONFIG_SYS_INIT_DCACHE_CS 7
366
367#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
368#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
369#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
370#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
371
372#endif
373