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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_P2041RDB
15#define CONFIG_PHYS_64BIT
16#define CONFIG_DISPLAY_BOARDINFO
17#define CONFIG_PPC_P2041
18
19#ifdef CONFIG_RAMBOOT_PBL
20#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
23#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
24#endif
25
26#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
27
28#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
29#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
30 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
31#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
32#define CONFIG_SYS_NO_FLASH
33#endif
34
35
36#define CONFIG_BOOKE
37#define CONFIG_E500
38#define CONFIG_E500MC
39#define CONFIG_SYS_BOOK3E_HV
40#define CONFIG_MP
41
42#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xeff40000
44#endif
45
46#ifndef CONFIG_RESET_VECTOR_ADDRESS
47#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48#endif
49
50#define CONFIG_SYS_FSL_CPC
51#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
52#define CONFIG_FSL_ELBC
53#define CONFIG_FSL_CAAM
54#define CONFIG_PCI
55#define CONFIG_PCIE1
56#define CONFIG_PCIE2
57#define CONFIG_PCIE3
58#define CONFIG_FSL_PCI_INIT
59#define CONFIG_SYS_PCI_64BIT
60
61#define CONFIG_SYS_SRIO
62#define CONFIG_SRIO1
63#define CONFIG_SRIO2
64#define CONFIG_SRIO_PCIE_BOOT_MASTER
65#define CONFIG_SYS_DPAA_RMAN
66
67#define CONFIG_FSL_LAW
68
69#define CONFIG_ENV_OVERWRITE
70
71#ifdef CONFIG_SYS_NO_FLASH
72#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
73#define CONFIG_ENV_IS_NOWHERE
74#endif
75#else
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_CFI
78#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
79#endif
80
81#if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000
89 #define CONFIG_ENV_OFFSET 0x100000
90 #define CONFIG_ENV_SECT_SIZE 0x10000
91#elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_FSL_FIXED_MMC_LOCATION
95 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (512 * 1658)
98#elif defined(CONFIG_NAND)
99#define CONFIG_SYS_EXTRA_ENV_RELOC
100#define CONFIG_ENV_IS_IN_NAND
101#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
102#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
103#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
104#define CONFIG_ENV_IS_IN_REMOTE
105#define CONFIG_ENV_ADDR 0xffe20000
106#define CONFIG_ENV_SIZE 0x2000
107#elif defined(CONFIG_ENV_IS_NOWHERE)
108#define CONFIG_ENV_SIZE 0x2000
109#else
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
112 - CONFIG_ENV_SECT_SIZE)
113 #define CONFIG_ENV_SIZE 0x2000
114 #define CONFIG_ENV_SECT_SIZE 0x20000
115#endif
116
117#ifndef __ASSEMBLY__
118unsigned long get_board_sys_clk(unsigned long dummy);
119#endif
120#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
121
122
123
124
125#define CONFIG_SYS_CACHE_STASHING
126#define CONFIG_BACKSIDE_L2_CACHE
127#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
128#define CONFIG_BTB
129
130#define CONFIG_ENABLE_36BIT_PHYS
131
132#ifdef CONFIG_PHYS_64BIT
133#define CONFIG_ADDR_MAP
134#define CONFIG_SYS_NUM_ADDR_MAP 64
135#endif
136
137#define CONFIG_POST CONFIG_SYS_POST_MEMORY
138#define CONFIG_SYS_MEMTEST_START 0x00200000
139#define CONFIG_SYS_MEMTEST_END 0x00400000
140#define CONFIG_SYS_ALT_MEMTEST
141#define CONFIG_PANIC_HANG
142
143
144
145
146#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
147#ifdef CONFIG_PHYS_64BIT
148#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
149 CONFIG_RAMBOOT_TEXT_BASE)
150#else
151#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
152#endif
153#define CONFIG_SYS_L3_SIZE (1024 << 10)
154#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
155
156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_DCSRBAR 0xf0000000
158#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
159#endif
160
161
162#define CONFIG_ID_EEPROM
163#define CONFIG_SYS_I2C_EEPROM_NXID
164#define CONFIG_SYS_EEPROM_BUS_NUM 0
165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167
168
169
170
171#define CONFIG_VERY_BIG_RAM
172#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
173#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
174
175#define CONFIG_DIMM_SLOTS_PER_CTLR 1
176#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
177
178#define CONFIG_DDR_SPD
179#define CONFIG_SYS_FSL_DDR3
180
181#define CONFIG_SYS_SPD_BUS_NUM 0
182#define SPD_EEPROM_ADDRESS 0x52
183#define CONFIG_SYS_SDRAM_SIZE 4096
184
185
186
187
188
189
190#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
191
192
193
194
195
196
197#define CONFIG_SYS_FLASH_BASE 0xe0000000
198#ifdef CONFIG_PHYS_64BIT
199#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
200#else
201#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
202#endif
203
204#define CONFIG_SYS_FLASH_BR_PRELIM \
205 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
206 BR_PS_16 | BR_V)
207#define CONFIG_SYS_FLASH_OR_PRELIM \
208 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
209 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
210
211#define CONFIG_FSL_CPLD
212#define CPLD_BASE 0xffdf0000
213#ifdef CONFIG_PHYS_64BIT
214#define CPLD_BASE_PHYS 0xfffdf0000ull
215#else
216#define CPLD_BASE_PHYS CPLD_BASE
217#endif
218
219#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
220#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
221
222#define PIXIS_LBMAP_SWITCH 7
223#define PIXIS_LBMAP_MASK 0xf0
224#define PIXIS_LBMAP_SHIFT 4
225#define PIXIS_LBMAP_ALTBANK 0x40
226
227#define CONFIG_SYS_FLASH_QUIET_TEST
228#define CONFIG_FLASH_SHOW_PROGRESS 45
229
230#define CONFIG_SYS_MAX_FLASH_BANKS 1
231#define CONFIG_SYS_MAX_FLASH_SECT 1024
232#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500
234
235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
236
237#if defined(CONFIG_RAMBOOT_PBL)
238#define CONFIG_SYS_RAMBOOT
239#endif
240
241#define CONFIG_NAND_FSL_ELBC
242
243#ifdef CONFIG_NAND_FSL_ELBC
244#define CONFIG_SYS_NAND_BASE 0xffa00000
245#ifdef CONFIG_PHYS_64BIT
246#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
247#else
248#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249#endif
250
251#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
252#define CONFIG_SYS_MAX_NAND_DEVICE 1
253#define CONFIG_CMD_NAND
254#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
255
256
257#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
258 | (2<<BR_DECC_SHIFT) \
259 | BR_PS_8 \
260 | BR_MS_FCM \
261 | BR_V)
262#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
263 | OR_FCM_PGS \
264 | OR_FCM_CSCT \
265 | OR_FCM_CST \
266 | OR_FCM_CHT \
267 | OR_FCM_SCY_1 \
268 | OR_FCM_TRLX \
269 | OR_FCM_EHTR)
270
271#ifdef CONFIG_NAND
272#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
273#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
274#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
275#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
276#else
277#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
278#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
279#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
280#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
281#endif
282#else
283#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
284#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
285#endif
286
287#define CONFIG_SYS_FLASH_EMPTY_INFO
288#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
289#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
290
291#define CONFIG_BOARD_EARLY_INIT_F
292#define CONFIG_BOARD_EARLY_INIT_R
293#define CONFIG_MISC_INIT_R
294
295#define CONFIG_HWCONFIG
296
297
298#define CONFIG_L1_INIT_RAM
299#define CONFIG_SYS_INIT_RAM_LOCK
300#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
301#ifdef CONFIG_PHYS_64BIT
302#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
303#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
304
305#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
306 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
307 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
308#else
309#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
310#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
311#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
312#endif
313#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
314
315#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
316 GENERATED_GBL_DATA_SIZE)
317#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
318
319#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
320#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
321
322
323
324
325
326#define CONFIG_CONS_INDEX 1
327#define CONFIG_SYS_NS16550_SERIAL
328#define CONFIG_SYS_NS16550_REG_SIZE 1
329#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
330
331#define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
333
334#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
335#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
336#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
337#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
338
339
340#define CONFIG_SYS_HUSH_PARSER
341
342
343#define CONFIG_OF_LIBFDT
344#define CONFIG_OF_BOARD_SETUP
345#define CONFIG_OF_STDOUT_VIA_ALIAS
346
347
348#define CONFIG_FIT
349#define CONFIG_FIT_VERBOSE
350
351
352#define CONFIG_SYS_I2C
353#define CONFIG_SYS_I2C_FSL
354#define CONFIG_SYS_FSL_I2C_SPEED 400000
355#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
356#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
357#define CONFIG_SYS_FSL_I2C2_SPEED 400000
358#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
359#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
360
361
362
363
364#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
365#ifdef CONFIG_PHYS_64BIT
366#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
367#else
368#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
369#endif
370#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
371
372#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
373#ifdef CONFIG_PHYS_64BIT
374#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
375#else
376#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
377#endif
378#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
379
380
381
382
383
384#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
385#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
386#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
387#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
388
389
390
391
392#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
393#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
394#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
395
396
397#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
398#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
399
400
401
402
403#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
404#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
405#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
406 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
407#endif
408
409
410
411
412#define CONFIG_CMD_SF
413#define CONFIG_SF_DEFAULT_SPEED 10000000
414#define CONFIG_SF_DEFAULT_MODE 0
415
416
417
418
419
420
421
422#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
423#ifdef CONFIG_PHYS_64BIT
424#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
425#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
426#else
427#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
428#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
429#endif
430#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
431#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
432#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
433#ifdef CONFIG_PHYS_64BIT
434#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
435#else
436#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
437#endif
438#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
439
440
441#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
442#ifdef CONFIG_PHYS_64BIT
443#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
444#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
445#else
446#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
447#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
448#endif
449#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
450#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
451#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
452#ifdef CONFIG_PHYS_64BIT
453#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
454#else
455#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
456#endif
457#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
458
459
460#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
461#ifdef CONFIG_PHYS_64BIT
462#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
463#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
464#else
465#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
466#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
467#endif
468#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
469#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
470#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
471#ifdef CONFIG_PHYS_64BIT
472#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
473#else
474#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
475#endif
476#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
477
478
479#define CONFIG_SYS_DPAA_QBMAN
480#define CONFIG_SYS_BMAN_NUM_PORTALS 10
481#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
482#ifdef CONFIG_PHYS_64BIT
483#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
484#else
485#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
486#endif
487#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
488#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
489#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
490#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
491#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
492#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
493 CONFIG_SYS_BMAN_CENA_SIZE)
494#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
495#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
496#define CONFIG_SYS_QMAN_NUM_PORTALS 10
497#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
498#ifdef CONFIG_PHYS_64BIT
499#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
500#else
501#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
502#endif
503#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
504#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
505#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
506#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
507#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
508#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
509 CONFIG_SYS_QMAN_CENA_SIZE)
510#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
511#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
512
513#define CONFIG_SYS_DPAA_FMAN
514#define CONFIG_SYS_DPAA_PME
515
516#if defined(CONFIG_SPIFLASH)
517
518
519
520
521#define CONFIG_SYS_QE_FW_IN_SPIFLASH
522#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
523#elif defined(CONFIG_SDCARD)
524
525
526
527
528
529#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
530#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
531#elif defined(CONFIG_NAND)
532#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
533#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
534#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
535
536
537
538
539
540
541
542#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
543#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
544#else
545#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
546#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
547#endif
548#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
549#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
550
551#ifdef CONFIG_SYS_DPAA_FMAN
552#define CONFIG_FMAN_ENET
553#define CONFIG_PHYLIB_10G
554#define CONFIG_PHY_VITESSE
555#define CONFIG_PHY_TERANETICS
556#endif
557
558#ifdef CONFIG_PCI
559#define CONFIG_PCI_INDIRECT_BRIDGE
560#define CONFIG_PCI_PNP
561
562#define CONFIG_PCI_SCAN_SHOW
563#define CONFIG_DOS_PARTITION
564#endif
565
566
567#define CONFIG_FSL_SATA_V2
568
569#ifdef CONFIG_FSL_SATA_V2
570#define CONFIG_FSL_SATA
571#define CONFIG_LIBATA
572
573#define CONFIG_SYS_SATA_MAX_DEVICE 2
574#define CONFIG_SATA1
575#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
576#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
577#define CONFIG_SATA2
578#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
579#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
580
581#define CONFIG_LBA48
582#define CONFIG_CMD_SATA
583#define CONFIG_DOS_PARTITION
584#define CONFIG_CMD_EXT2
585#endif
586
587#ifdef CONFIG_FMAN_ENET
588#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
589#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
590#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
591#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
592#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
593
594#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
595#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
596#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
597#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
598
599#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
600
601#define CONFIG_SYS_TBIPA_VALUE 8
602#define CONFIG_MII
603#define CONFIG_ETHPRIME "FM1@DTSEC1"
604#define CONFIG_PHY_GIGE
605#endif
606
607
608
609
610#define CONFIG_LOADS_ECHO
611#define CONFIG_SYS_LOADS_BAUD_CHANGE
612
613
614
615
616#define CONFIG_CMD_DHCP
617#define CONFIG_CMD_ERRATA
618#define CONFIG_CMD_GREPENV
619#define CONFIG_CMD_IRQ
620#define CONFIG_CMD_I2C
621#define CONFIG_CMD_MII
622#define CONFIG_CMD_PING
623
624#ifdef CONFIG_PCI
625#define CONFIG_CMD_PCI
626#endif
627
628
629
630
631#define CONFIG_HAS_FSL_DR_USB
632#define CONFIG_HAS_FSL_MPH_USB
633
634#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
635#define CONFIG_CMD_USB
636#define CONFIG_USB_STORAGE
637#define CONFIG_USB_EHCI
638#define CONFIG_USB_EHCI_FSL
639#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
640#endif
641
642#define CONFIG_CMD_EXT2
643
644#define CONFIG_MMC
645
646#ifdef CONFIG_MMC
647#define CONFIG_FSL_ESDHC
648#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
649#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
650#define CONFIG_CMD_MMC
651#define CONFIG_GENERIC_MMC
652#define CONFIG_CMD_EXT2
653#define CONFIG_CMD_FAT
654#define CONFIG_DOS_PARTITION
655#endif
656
657
658#ifdef CONFIG_FSL_CAAM
659#define CONFIG_CMD_HASH
660#define CONFIG_SHA_HW_ACCEL
661#endif
662
663
664
665
666#define CONFIG_SYS_LONGHELP
667#define CONFIG_CMDLINE_EDITING
668#define CONFIG_AUTO_COMPLETE
669#define CONFIG_SYS_LOAD_ADDR 0x2000000
670#ifdef CONFIG_CMD_KGDB
671#define CONFIG_SYS_CBSIZE 1024
672#else
673#define CONFIG_SYS_CBSIZE 256
674#endif
675
676#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
677 sizeof(CONFIG_SYS_PROMPT)+16)
678#define CONFIG_SYS_MAXARGS 16
679
680#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
681
682
683
684
685
686
687#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
688#define CONFIG_SYS_BOOTM_LEN (64 << 20)
689
690#ifdef CONFIG_CMD_KGDB
691#define CONFIG_KGDB_BAUDRATE 230400
692#endif
693
694
695
696
697#define CONFIG_ROOTPATH "/opt/nfsroot"
698#define CONFIG_BOOTFILE "uImage"
699#define CONFIG_UBOOTPATH u-boot.bin
700
701
702#define CONFIG_LOADADDR 1000000
703
704#define CONFIG_BOOTDELAY 10
705
706#define CONFIG_BAUDRATE 115200
707
708#define __USB_PHY_TYPE utmi
709
710#define CONFIG_EXTRA_ENV_SETTINGS \
711 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
712 "bank_intlv=cs0_cs1\0" \
713 "netdev=eth0\0" \
714 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
715 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
716 "tftpflash=tftpboot $loadaddr $uboot && " \
717 "protect off $ubootaddr +$filesize && " \
718 "erase $ubootaddr +$filesize && " \
719 "cp.b $loadaddr $ubootaddr $filesize && " \
720 "protect on $ubootaddr +$filesize && " \
721 "cmp.b $loadaddr $ubootaddr $filesize\0" \
722 "consoledev=ttyS0\0" \
723 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
724 "usb_dr_mode=host\0" \
725 "ramdiskaddr=2000000\0" \
726 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
727 "fdtaddr=c00000\0" \
728 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
729 "bdev=sda3\0"
730
731#define CONFIG_HDBOOT \
732 "setenv bootargs root=/dev/$bdev rw " \
733 "console=$consoledev,$baudrate $othbootargs;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr - $fdtaddr"
737
738#define CONFIG_NFSBOOTCOMMAND \
739 "setenv bootargs root=/dev/nfs rw " \
740 "nfsroot=$serverip:$rootpath " \
741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "tftp $loadaddr $bootfile;" \
744 "tftp $fdtaddr $fdtfile;" \
745 "bootm $loadaddr - $fdtaddr"
746
747#define CONFIG_RAMBOOTCOMMAND \
748 "setenv bootargs root=/dev/ram rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $ramdiskaddr $ramdiskfile;" \
751 "tftp $loadaddr $bootfile;" \
752 "tftp $fdtaddr $fdtfile;" \
753 "bootm $loadaddr $ramdiskaddr $fdtaddr"
754
755#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
756
757#include <asm/fsl_secure_boot.h>
758
759#ifdef CONFIG_SECURE_BOOT
760#define CONFIG_CMD_BLOB
761#endif
762
763#endif
764