1/* 2 * (C) Copyright 2003 3 * Denis Peter d.peter@mpl.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * File: PATI.h 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 */ 18 19#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 20#define CONFIG_PATI 1 /* ...On a PATI board */ 21 22#define CONFIG_SYS_TEXT_BASE 0xFFF00000 23 24 25/* Serial Console Configuration */ 26#define CONFIG_5xx_CONS_SCI1 27#undef CONFIG_5xx_CONS_SCI2 28 29#define CONFIG_BAUDRATE 9600 30 31 32/* 33 * BOOTP options 34 */ 35#define CONFIG_BOOTP_BOOTFILESIZE 36#define CONFIG_BOOTP_BOOTPATH 37#define CONFIG_BOOTP_GATEWAY 38#define CONFIG_BOOTP_HOSTNAME 39 40 41/* 42 * Command line configuration. 43 */ 44#define CONFIG_CMD_REGINFO 45#define CONFIG_CMD_REGINFO 46#define CONFIG_CMD_BSP 47#define CONFIG_CMD_EEPROM 48#define CONFIG_CMD_IRQ 49 50 51#if 0 52#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 53#else 54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 55#endif 56#define CONFIG_BOOTCOMMAND "" /* autoboot command */ 57 58#define CONFIG_BOOTARGS "" /* */ 59 60#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 61 62/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ 63 64#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 65 66/* 67 * Miscellaneous configurable options 68 */ 69#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ 70#define CONFIG_PREBOOT 71 72#define CONFIG_SYS_LONGHELP /* undef to save memory */ 73#if defined(CONFIG_CMD_KGDB) 74#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 75#else 76#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 77#endif 78#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 79#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 80#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 81 82#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 83#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 84 85#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 86 87#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 88 89#define CONFIG_BOARD_EARLY_INIT_F 90 91/*********************************************************************** 92 * Last Stage Init 93 ***********************************************************************/ 94#define CONFIG_LAST_STAGE_INIT 95 96/* 97 * Low Level Configuration Settings 98 */ 99 100/* 101 * Internal Memory Mapped (This is not the IMMR content) 102 */ 103#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 104 105/* 106 * Definitions for initial stack pointer and data area 107 */ 108#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 109#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 110#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 111#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 112/* 113 * Start addresses for the final memory configuration 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 115 */ 116#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 117#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 118#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 119#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 120#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 121 122#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 123/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 124 /* This adress is given to the linker with -Ttext to */ 125 /* locate the text section at this adress. */ 126#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 127#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 128 129#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 130 131/* 132 * For booting Linux, the board info and command line data 133 * have to be in the first 8 MB of memory, since this is 134 * the maximum mapped by the Linux kernel during initialization. 135 */ 136#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 137 138 139/*----------------------------------------------------------------------- 140 * FLASH organization 141 *----------------------------------------------------------------------- 142 * 143 */ 144 145#define CONFIG_SYS_FLASH_PROTECTION 146#define CONFIG_SYS_FLASH_EMPTY_INFO 147 148#define CONFIG_SYS_FLASH_CFI 149#define CONFIG_FLASH_CFI_DRIVER 150 151#define CONFIG_FLASH_SHOW_PROGRESS 45 152 153#define CONFIG_SYS_MAX_FLASH_BANKS 1 154#define CONFIG_SYS_MAX_FLASH_SECT 128 155 156#define CONFIG_ENV_IS_IN_EEPROM 157#ifdef CONFIG_ENV_IS_IN_EEPROM 158#define CONFIG_ENV_OFFSET 0 159#define CONFIG_ENV_SIZE 2048 160#endif 161 162#undef CONFIG_ENV_IS_IN_FLASH 163#ifdef CONFIG_ENV_IS_IN_FLASH 164#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 165#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 166#endif 167 168 169#define CONFIG_SPI 1 170#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 171#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 172#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 173/*----------------------------------------------------------------------- 174 * SYPCR - System Protection Control 175 * SYPCR can only be written once after reset! 176 *----------------------------------------------------------------------- 177 * SW Watchdog freeze 178 */ 179#undef CONFIG_WATCHDOG 180#if defined(CONFIG_WATCHDOG) 181#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 182 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 183#else 184#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 185 SYPCR_SWP) 186#endif /* CONFIG_WATCHDOG */ 187 188/*----------------------------------------------------------------------- 189 * TBSCR - Time Base Status and Control 190 *----------------------------------------------------------------------- 191 * Clear Reference Interrupt Status, Timebase freezing enabled 192 */ 193#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 194 195/*----------------------------------------------------------------------- 196 * PISCR - Periodic Interrupt Status and Control 197 *----------------------------------------------------------------------- 198 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 199 */ 200#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 201 202/*----------------------------------------------------------------------- 203 * SCCR - System Clock and reset Control Register 204 *----------------------------------------------------------------------- 205 * Set clock output, timebase and RTC source and divider, 206 * power management and some other internal clocks 207 */ 208#define SCCR_MASK SCCR_EBDF00 209#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 210 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 211 212/*----------------------------------------------------------------------- 213 * SIUMCR - SIU Module Configuration 214 *----------------------------------------------------------------------- 215 * Data show cycle 216 */ 217#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 218 219/*----------------------------------------------------------------------- 220 * PLPRCR - PLL, Low-Power, and Reset Control Register 221 *----------------------------------------------------------------------- 222 * Set all bits to 40 Mhz 223 * 224 */ 225#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 226 227 228#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 229 230/*----------------------------------------------------------------------- 231 * UMCR - UIMB Module Configuration Register 232 *----------------------------------------------------------------------- 233 * 234 */ 235#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 236 237/*----------------------------------------------------------------------- 238 * ICTRL - I-Bus Support Control Register 239 */ 240#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 241 242/*----------------------------------------------------------------------- 243 * USIU - Memory Controller Register 244 *----------------------------------------------------------------------- 245 */ 246#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 247#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 248/* SDRAM */ 249#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 250#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 251/* PCI */ 252#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 253#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 254/* config registers: */ 255#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 256#define CONFIG_SYS_OR3_PRELIM (0xffff0000) 257 258#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 259 260/*----------------------------------------------------------------------- 261 * DER - Timer Decrementer 262 *----------------------------------------------------------------------- 263 * Initialise to zero 264 */ 265#define CONFIG_SYS_DER 0x00000000 266 267#define VERSION_TAG "released" 268#define CONFIG_ISO_STRING "MEV-10084-001" 269 270#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG 271 272#endif /* __CONFIG_H */ 273