uboot/include/configs/VCMA9.h
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   1/*
   2 * (C) Copyright 2002, 2003
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 * Gary Jennejohn <garyj@denx.de>
   6 * David Mueller <d.mueller@elsoft.ch>
   7 *
   8 * Configuation settings for the MPL VCMA9 board.
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#ifndef __CONFIG_H
  14#define __CONFIG_H
  15
  16
  17#define MACH_TYPE_MPL_VCMA9     227
  18
  19/*
  20 * High Level Configuration Options
  21 * (easy to change)
  22 */
  23#define CONFIG_S3C24X0          /* This is a SAMSUNG S3C24x0-type SoC */
  24#define CONFIG_S3C2410          /* specifically a SAMSUNG S3C2410 SoC */
  25#define CONFIG_VCMA9            /* on a MPL VCMA9 Board  */
  26#define CONFIG_MACH_TYPE        MACH_TYPE_MPL_VCMA9 /* Machine type */
  27
  28#define CONFIG_SYS_TEXT_BASE    0x0
  29
  30
  31#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
  32
  33/* input clock of PLL (VCMA9 has 12MHz input clock) */
  34#define CONFIG_SYS_CLK_FREQ     12000000
  35
  36#define CONFIG_CMDLINE_TAG      /* enable passing of ATAGs */
  37#define CONFIG_SETUP_MEMORY_TAGS
  38#define CONFIG_INITRD_TAG
  39
  40/*
  41 * BOOTP options
  42 */
  43#define CONFIG_BOOTP_BOOTFILESIZE
  44#define CONFIG_BOOTP_BOOTPATH
  45#define CONFIG_BOOTP_GATEWAY
  46#define CONFIG_BOOTP_HOSTNAME
  47
  48/*
  49 * Command line configuration.
  50 */
  51#define CONFIG_CMD_CACHE
  52#define CONFIG_CMD_EEPROM
  53#define CONFIG_CMD_I2C
  54#define CONFIG_CMD_USB
  55#define CONFIG_CMD_REGINFO
  56#define CONFIG_CMD_DATE
  57#define CONFIG_CMD_DHCP
  58#define CONFIG_CMD_PING
  59#define CONFIG_CMD_BSP
  60#define CONFIG_CMD_NAND
  61
  62#define CONFIG_BOARD_LATE_INIT
  63
  64#define CONFIG_SYS_HUSH_PARSER
  65#define CONFIG_CMDLINE_EDITING
  66
  67/*
  68 * I2C stuff:
  69 * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  70 * address 0x50 with 16bit addressing
  71 */
  72#define CONFIG_SYS_I2C
  73
  74/* we use the built-in I2C controller */
  75#define CONFIG_SYS_I2C_S3C24X0
  76#define CONFIG_SYS_I2C_S3C24X0_SPEED    100000  /* I2C speed */
  77#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x7F    /* I2C slave addr */
  78
  79#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
  80#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  81/* use EEPROM for environment vars */
  82#define CONFIG_ENV_IS_IN_EEPROM         1
  83/* environment starts at offset 0 */
  84#define CONFIG_ENV_OFFSET               0x000
  85/* 2KB should be more than enough */
  86#define CONFIG_ENV_SIZE                 0x800
  87
  88#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  89/* 64 bytes page write mode on 24C256 */
  90#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  91#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  92
  93/*
  94 * Hardware drivers
  95 */
  96#define CONFIG_CS8900                   /* we have a CS8900 on-board */
  97#define CONFIG_CS8900_BASE              0x20000300
  98#define CONFIG_CS8900_BUS16
  99
 100/*
 101 * select serial console configuration
 102 */
 103#define CONFIG_S3C24X0_SERIAL
 104#define CONFIG_SERIAL1          1       /* we use SERIAL 1 on VCMA9 */
 105
 106/* USB support (currently only works with D-cache off) */
 107#define CONFIG_USB_OHCI
 108#define CONFIG_USB_OHCI_S3C24XX
 109#define CONFIG_USB_KEYBOARD
 110#define CONFIG_USB_STORAGE
 111#define CONFIG_DOS_PARTITION
 112
 113/* Enable needed helper functions */
 114#define CONFIG_SYS_STDIO_DEREGISTER     /* needs stdio_deregister */
 115
 116/* RTC */
 117#define CONFIG_RTC_S3C24X0
 118
 119
 120/* allow to overwrite serial and ethaddr */
 121#define CONFIG_ENV_OVERWRITE
 122
 123#define CONFIG_BAUDRATE                 9600
 124
 125#define CONFIG_BOOTDELAY                5
 126#define CONFIG_BOOT_RETRY_TIME          -1
 127#define CONFIG_RESET_TO_RETRY
 128#define CONFIG_ZERO_BOOTDELAY_CHECK
 129
 130#define CONFIG_NETMASK                  255.255.255.0
 131#define CONFIG_IPADDR                   10.0.0.110
 132#define CONFIG_SERVERIP                 10.0.0.1
 133
 134#if defined(CONFIG_CMD_KGDB)
 135/* speed to run kgdb serial port */
 136#define CONFIG_KGDB_BAUDRATE            115200
 137#endif
 138
 139/* Miscellaneous configurable options */
 140#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 141#define CONFIG_SYS_CBSIZE               256
 142/* Print Buffer Size */
 143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 144#define CONFIG_SYS_MAXARGS              16
 145/* Boot Argument Buffer Size */
 146#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 147
 148#define CONFIG_DISPLAY_CPUINFO                          /* Display cpu info */
 149#define CONFIG_DISPLAY_BOARDINFO                        /* Display board info */
 150
 151#define CONFIG_SYS_MEMTEST_START        0x30000000      /* memtest works on */
 152#define CONFIG_SYS_MEMTEST_END          0x31FFFFFF      /* 32 MB in DRAM */
 153
 154#define CONFIG_SYS_ALT_MEMTEST
 155#define CONFIG_SYS_LOAD_ADDR            0x30800000
 156
 157/* we configure PWM Timer 4 to 1ms 1000Hz  */
 158
 159/* support additional compression methods */
 160#define CONFIG_BZIP2
 161#define CONFIG_LZO
 162#define CONFIG_LZMA
 163
 164/* Ident */
 165/*#define VERSION_TAG "released"*/
 166#define VERSION_TAG "unstable"
 167#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
 168                            "MEV-10080-001 " VERSION_TAG
 169
 170/* Physical Memory Map */
 171#define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 172#define PHYS_SDRAM_1            0x30000000      /* SDRAM Bank #1 */
 173#define PHYS_FLASH_1            0x00000000      /* Flash Bank #1 */
 174
 175#define CONFIG_SYS_FLASH_BASE   PHYS_FLASH_1
 176
 177/* FLASH and environment organization */
 178
 179#define CONFIG_SYS_FLASH_CFI
 180#define CONFIG_FLASH_CFI_DRIVER
 181#define CONFIG_FLASH_CFI_LEGACY
 182#define CONFIG_SYS_FLASH_LEGACY_512Kx16
 183#define CONFIG_FLASH_SHOW_PROGRESS      45
 184#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 185#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 186#define CONFIG_SYS_MAX_FLASH_SECT       (19)
 187
 188/*
 189 * Size of malloc() pool
 190 * BZIP2 / LZO / LZMA need a lot of RAM
 191 */
 192#define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 193#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 194#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 195
 196/* NAND configuration */
 197#ifdef CONFIG_CMD_NAND
 198#define CONFIG_NAND_S3C2410
 199#define CONFIG_SYS_S3C2410_NAND_HWECC
 200#define CONFIG_SYS_MAX_NAND_DEVICE      1
 201#define CONFIG_SYS_NAND_BASE            0x4E000000
 202#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
 203#define CONFIG_S3C24XX_TACLS            1
 204#define CONFIG_S3C24XX_TWRPH0           5
 205#define CONFIG_S3C24XX_TWRPH1           3
 206#endif
 207
 208#define MULTI_PURPOSE_SOCKET_ADDR       0x08000000
 209
 210/* File system */
 211#define CONFIG_CMD_FAT
 212#define CONFIG_CMD_UBI
 213#define CONFIG_CMD_UBIFS
 214#define CONFIG_CMD_JFFS2
 215#define CONFIG_YAFFS2
 216#define CONFIG_RBTREE
 217#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 218#define CONFIG_MTD_PARTITIONS
 219#define CONFIG_CMD_MTDPARTS
 220#define CONFIG_LZO
 221
 222#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 223#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 224                                        GENERATED_GBL_DATA_SIZE)
 225
 226#define CONFIG_BOARD_EARLY_INIT_F
 227
 228#endif /* __CONFIG_H */
 229