LXR uboot/include/configs/intip.h

   1/*
   2 * (C) Copyright 2009
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * Based on include/configs/canyonlands.h
   6 * (C) Copyright 2008
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12/*
  13 * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
  14 */
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*
  19 * High Level Configuration Options
  20 */
  21/*
  22 * This config file is used for CompactCenter(codename intip) and DevCon-Center
  23 */
  24#define CONFIG_460EX            1       /* Specific PPC460EX            */
  25#ifdef CONFIG_DEVCONCENTER
  26#define CONFIG_HOSTNAME         devconcenter
  27#define CONFIG_IDENT_STRING     " devconcenter 0.06"
  28#else
  29#define CONFIG_HOSTNAME         intip
  30#define CONFIG_IDENT_STRING     " intip 0.06"
  31#endif
  32#define CONFIG_440              1
  33
  34#ifndef CONFIG_SYS_TEXT_BASE
  35#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  36#endif
  37
  38/*
  39 * Include common defines/options for all AMCC eval boards
  40 */
  41#include "amcc-common.h"
  42
  43#define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  44
  45#define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  46#define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  47#define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  48#define CONFIG_BOARD_TYPES              1       /* support board types */
  49#define CONFIG_FIT
  50#define CFG_ALT_MEMTEST
  51
  52#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
  53
  54/*
  55 * Base addresses -- Note these are effective addresses where the
  56 * actual resources get mapped (not physical addresses)
  57 */
  58#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory */
  59#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs */
  60#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  61
  62/* EBC stuff */
  63#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
  64#define CONFIG_SYS_FLASH_BASE           0xF8000000      /* later mapped here */
  65#define CONFIG_SYS_FLASH_SIZE           (128 << 20)
  66#else
  67#define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped here */
  68#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  69#endif
  70
  71#define CONFIG_SYS_NVRAM_BASE           0xE0000000
  72#define CONFIG_SYS_UART_BASE            0xE0100000
  73#define CONFIG_SYS_IO_BASE              0xE0200000
  74
  75#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
  76#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
  77#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
  78#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xC8000000
  79#else
  80#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
  81#endif
  82#define CONFIG_SYS_FLASH_BASE_PHYS \
  83        (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
  84        | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
  85
  86#define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k */
  87#define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k */
  88#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
  89#define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
  90
  91#define CONFIG_SYS_AHB_BASE             0xE2000000      /* int. AHB periph. */
  92
  93/*
  94 * Initial RAM & stack pointer (placed in OCM)
  95 */
  96#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM */
  97#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  98#define CONFIG_SYS_GBL_DATA_OFFSET \
  99        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 100#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 101
 102/*
 103 * Serial Port
 104 */
 105#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 106
 107/*
 108 * Environment
 109 */
 110/*
 111 * Define here the location of the environment variables (FLASH).
 112 */
 113#define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 114#define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 115
 116/*
 117 * FLASH related
 118 */
 119#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 120#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 121#define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD reset cmd */
 122
 123#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 124#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 125#ifdef CONFIG_DEVCONCENTER
 126#define CONFIG_SYS_MAX_FLASH_SECT       1024    /* max num of sectors per chip*/
 127#else
 128#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 129#endif
 130
 131#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 132#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 133
 134#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buff'd writes (20x faster) */
 135#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 136
 137#ifdef CONFIG_ENV_IS_IN_FLASH
 138#define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector*/
 139#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 140#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector */
 141
 142/* Address and size of Redundant Environment Sector     */
 143#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 144#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 145#endif /* CONFIG_ENV_IS_IN_FLASH */
 146
 147/*
 148 * DDR SDRAM
 149 */
 150
 151#define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 152
 153#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 154#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 155#undef CONFIG_PPC4xx_DDR_METHOD_A
 156
 157/* DDR1/2 SDRAM Device Control Register Data Values */
 158/* Memory Queue */
 159#define CONFIG_SYS_SDRAM_R0BAS          0x0000f800
 160#define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 161#define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 162#define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 163#define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 164#define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 165#define CONFIG_SYS_SDRAM_CONF1LL        0x80001C00
 166#define CONFIG_SYS_SDRAM_CONF1HB        0x80001C80
 167#define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 168
 169/* SDRAM Controller */
 170#define CONFIG_SYS_SDRAM0_MB0CF         0x00000201
 171#define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 172#define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 173#define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 174#define CONFIG_SYS_SDRAM0_MCOPT1        0x05120000
 175#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 176#define CONFIG_SYS_SDRAM0_MODT0         0x00000000
 177#define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 178#define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 179#define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 180#define CONFIG_SYS_SDRAM0_CODT          0x00000020
 181#define CONFIG_SYS_SDRAM0_RTR           0x06180000
 182#define CONFIG_SYS_SDRAM0_INITPLR0      0xA8380000
 183#define CONFIG_SYS_SDRAM0_INITPLR1      0x81900400
 184#define CONFIG_SYS_SDRAM0_INITPLR2      0x81020000
 185#define CONFIG_SYS_SDRAM0_INITPLR3      0x81030000
 186#define CONFIG_SYS_SDRAM0_INITPLR4      0x81010002
 187#define CONFIG_SYS_SDRAM0_INITPLR5      0xE4000552
 188#define CONFIG_SYS_SDRAM0_INITPLR6      0x81900400
 189#define CONFIG_SYS_SDRAM0_INITPLR7      0x8A880000
 190#define CONFIG_SYS_SDRAM0_INITPLR8      0x8A880000
 191#define CONFIG_SYS_SDRAM0_INITPLR9      0x8A880000
 192#define CONFIG_SYS_SDRAM0_INITPLR10     0x8A880000
 193#define CONFIG_SYS_SDRAM0_INITPLR11     0x81000452
 194#define CONFIG_SYS_SDRAM0_INITPLR12     0x81010382
 195#define CONFIG_SYS_SDRAM0_INITPLR13     0x81010002
 196#define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 197#define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 198#define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 199#define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 200#define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 201#define CONFIG_SYS_SDRAM0_DLCR          0x00000000
 202#define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 203#define CONFIG_SYS_SDRAM0_WRDTR         0x86000823
 204#define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 205#define CONFIG_SYS_SDRAM0_SDTR2         0x32204232
 206#define CONFIG_SYS_SDRAM0_SDTR3         0x090C0D15
 207#define CONFIG_SYS_SDRAM0_MMODE         0x00000452
 208#define CONFIG_SYS_SDRAM0_MEMODE        0x00000002
 209
 210#define CONFIG_SYS_MBYTES_SDRAM 256     /* 256MB */
 211
 212/*
 213 * I2C
 214 */
 215#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 216
 217#define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 218#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 219#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 220#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 221
 222/* I2C bootstrap EEPROM */
 223#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 224#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 225#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 226
 227/* I2C SYSMON */
 228#define CONFIG_DTT_LM63         1       /* National LM63        */
 229#define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 230#define CONFIG_DTT_PWM_LOOKUPTABLE      \
 231        { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 232#define CONFIG_DTT_TACH_LIMIT   0xa10
 233
 234/* RTC configuration */
 235#define CONFIG_RTC_DS1337       1
 236#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 237
 238/*
 239 * Ethernet
 240 */
 241#define CONFIG_IBM_EMAC4_V4     1
 242
 243#define CONFIG_HAS_ETH0
 244#define CONFIG_HAS_ETH1
 245
 246#define CONFIG_PHY_ADDR         2       /* PHY address, See schematics  */
 247#define CONFIG_PHY1_ADDR        3
 248
 249#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 250#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 251#define CONFIG_PHY_DYNAMIC_ANEG 1
 252
 253/*
 254 * USB-OHCI
 255 */
 256#define CONFIG_USB_OHCI_NEW
 257#define CONFIG_USB_STORAGE
 258#undef CONFIG_SYS_OHCI_BE_CONTROLLER    /* 460EX has little endian descriptors*/
 259#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
 260#define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode */
 261#define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 262#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 263#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 264
 265/*
 266 * Default environment variables
 267 */
 268#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 269        CONFIG_AMCC_DEF_ENV                                             \
 270        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 271        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 272        "kernel_addr=fc000000\0"                                        \
 273        "fdt_addr=fc1e0000\0"                                           \
 274        "ramdisk_addr=fc200000\0"                                       \
 275        "pciconfighost=1\0"                                             \
 276        "pcie_mode=RP:RP\0"                                             \
 277        ""
 278
 279/*
 280 * Commands additional to the ones defined in amcc-common.h
 281 */
 282#define CONFIG_CMD_CHIP_CONFIG
 283#define CONFIG_CMD_DATE
 284#define CONFIG_CMD_DTT
 285#define CONFIG_CMD_EXT2
 286#define CONFIG_CMD_FAT
 287#define CONFIG_CMD_PCI
 288#define CONFIG_CMD_SDRAM
 289#define CONFIG_CMD_SNTP
 290#define CONFIG_CMD_USB
 291
 292/* Partitions */
 293#define CONFIG_MAC_PARTITION
 294#define CONFIG_DOS_PARTITION
 295#define CONFIG_ISO_PARTITION
 296
 297/*
 298 * PCI stuff
 299 */
 300/* General PCI */
 301#define CONFIG_PCI                      /* include pci support          */
 302#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 303#define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 304#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 305#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 306#define CONFIG_PCI_DISABLE_PCIE
 307
 308/* Board-specific PCI */
 309#define CONFIG_SYS_PCI_TARGET_INIT      /* let board init pci target */
 310#undef  CONFIG_SYS_PCI_MASTER_INIT
 311
 312#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM */
 313#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 314
 315
 316/*
 317 * External Bus Controller (EBC) Setup
 318 */
 319
 320/*
 321 * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 322 * boot EBC mapping only supports a maximum of 16MBytes
 323 * (4.ff00.0000 - 4.ffff.ffff).
 324 * To solve this problem, the FLASH has to get remapped to another
 325 * EBC address which accepts bigger regions:
 326 *
 327 * 0xfc00.0000 -> 4.cc00.0000
 328 */
 329
 330
 331/* Memory Bank 0 (NOR-FLASH) initialization */
 332#define CONFIG_SYS_EBC_PB0AP            0x10055e00
 333#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 334
 335/* Memory Bank 1 (NVRAM) initialization */
 336#define CONFIG_SYS_EBC_PB1AP            0x02815480
 337/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
 338#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NVRAM_BASE | 0x18000)
 339
 340/* Memory Bank 2 (UART) initialization  */
 341#define CONFIG_SYS_EBC_PB2AP            0x02815480
 342/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
 343#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_UART_BASE | 0x1A000)
 344
 345/* Memory Bank 3 (IO) initialization */
 346#define CONFIG_SYS_EBC_PB3AP            0x02815480
 347/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
 348#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_IO_BASE | 0x1A000)
 349
 350/*
 351 * PPC4xx GPIO Configuration
 352 */
 353/* 460EX: Use USB configuration */
 354#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 355{                                                                                       \
 356/* GPIO Core 0 */                                                                       \
 357{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 358{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 359{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 360{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 361{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 362{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 363{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 364{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 365{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 366{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 367{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 368{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 369{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 370{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 371{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 372{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 373{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 374{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 375{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 376{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 377{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 378{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 379{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 380{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 381{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 382{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 383{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 384{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 385{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 386{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 387{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 388{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 389},                                                                                      \
 390{                                                                                       \
 391/* GPIO Core 1 */                                                                       \
 392{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 393{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 394{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 395{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 396{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 397{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 398{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 399{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 400{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 401{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 402{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 403{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 404{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 405{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 406{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 407{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 408{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 409{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 410{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  USB_SERVICE_SUSPEND_N         */      \
 411{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51  SPI_CSS_N                     */      \
 412{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52  FPGA_PROGRAM_UC_N             */      \
 413{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  FPGA_INIT_UC_N                */      \
 414{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54  WD_STROBE                     */      \
 415{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  LED_2_OUT                     */      \
 416{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56  LED_1_OUT                     */      \
 417{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 418{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 419{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 420{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 421{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61  STARTUP_FINISHED_N            */      \
 422{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62  STARTUP_FINISHED              */      \
 423{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  SERVICE_PORT_ACTIVE           */      \
 424}                                                                                       \
 425}
 426
 427#endif  /* __CONFIG_H */
 428