1/* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __SH7785LCR_H 10#define __SH7785LCR_H 11 12#undef DEBUG 13#define CONFIG_CPU_SH7785 1 14#define CONFIG_SH7785LCR 1 15 16#define CONFIG_CMD_PCI 17#define CONFIG_CMD_PING 18#define CONFIG_CMD_SDRAM 19#define CONFIG_CMD_SH_ZIMAGEBOOT 20 21#define CONFIG_CMD_USB 22#define CONFIG_USB_STORAGE 23#define CONFIG_CMD_EXT2 24#define CONFIG_CMD_FAT 25#define CONFIG_DOS_PARTITION 26#define CONFIG_MAC_PARTITION 27 28#define CONFIG_BAUDRATE 115200 29#define CONFIG_BOOTDELAY 3 30#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 31 32#define CONFIG_EXTRA_ENV_SETTINGS \ 33 "bootdevice=0:1\0" \ 34 "usbload=usb reset;usbboot;usb stop;bootm\0" 35 36#define CONFIG_VERSION_VARIABLE 37#undef CONFIG_SHOW_BOOT_PROGRESS 38 39/* MEMORY */ 40#if defined(CONFIG_SH_32BIT) 41#define CONFIG_SYS_TEXT_BASE 0x8FF80000 42/* 0x40000000 - 0x47FFFFFF does not use */ 43#define CONFIG_SH_SDRAM_OFFSET (0x8000000) 44#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 45#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 46#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 47#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 48#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 49#define SH7785LCR_USB_BASE (0xa6000000) 50#else 51#define CONFIG_SYS_TEXT_BASE 0x0FF80000 52#define SH7785LCR_SDRAM_BASE (0x08000000) 53#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 54#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 55#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 56#define SH7785LCR_USB_BASE (0xb4000000) 57#endif 58 59#define CONFIG_SYS_LONGHELP 60#define CONFIG_SYS_CBSIZE 256 61#define CONFIG_SYS_PBSIZE 256 62#define CONFIG_SYS_MAXARGS 16 63#define CONFIG_SYS_BARGSIZE 512 64#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 65 66/* SCIF */ 67#define CONFIG_SCIF_CONSOLE 1 68#define CONFIG_CONS_SCIF1 1 69#define CONFIG_SCIF_EXT_CLOCK 1 70#undef CONFIG_SYS_CONSOLE_INFO_QUIET 71#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 72#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 73 74 75#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 76#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 77 (SH7785LCR_SDRAM_SIZE) - \ 78 4 * 1024 * 1024) 79#undef CONFIG_SYS_ALT_MEMTEST 80#undef CONFIG_SYS_MEMTEST_SCRATCH 81#undef CONFIG_SYS_LOADS_BAUD_CHANGE 82 83#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 84#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 85#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 86 87#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 88#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 89#define CONFIG_SYS_MALLOC_LEN (512 * 1024) 90#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 91 92/* FLASH */ 93#define CONFIG_FLASH_CFI_DRIVER 94#define CONFIG_SYS_FLASH_CFI 95#undef CONFIG_SYS_FLASH_QUIET_TEST 96#define CONFIG_SYS_FLASH_EMPTY_INFO 97#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 98#define CONFIG_SYS_MAX_FLASH_SECT 512 99 100#define CONFIG_SYS_MAX_FLASH_BANKS 1 101#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 102 (0 * SH7785LCR_FLASH_BANK_SIZE) } 103 104#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 105#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 106#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 107#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 108 109#undef CONFIG_SYS_FLASH_PROTECTION 110#undef CONFIG_SYS_DIRECT_FLASH_TFTP 111 112/* R8A66597 */ 113#define CONFIG_USB_R8A66597_HCD 114#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 115#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 116#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 117#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 118 119/* PCI Controller */ 120#define CONFIG_PCI 121#define CONFIG_SH4_PCI 122#define CONFIG_SH7780_PCI 123#if defined(CONFIG_SH_32BIT) 124#define CONFIG_SH7780_PCI_LSR 0x1ff00001 125#define CONFIG_SH7780_PCI_LAR 0x5f000000 126#define CONFIG_SH7780_PCI_BAR 0x5f000000 127#else 128#define CONFIG_SH7780_PCI_LSR 0x07f00001 129#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 130#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 131#endif 132#define CONFIG_PCI_PNP 133#define CONFIG_PCI_SCAN_SHOW 1 134 135#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 136#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 137#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 138 139#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 140#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 141#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 142 143#if defined(CONFIG_SH_32BIT) 144#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 145#else 146#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 147#endif 148#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 149#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 150 151/* Network device (RTL8169) support */ 152#define CONFIG_RTL8169 153 154/* ENV setting */ 155#define CONFIG_ENV_IS_IN_FLASH 156#define CONFIG_ENV_OVERWRITE 1 157#define CONFIG_ENV_SECT_SIZE (256 * 1024) 158#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 159#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 160#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 161#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 162 163/* Board Clock */ 164/* The SCIF used external clock. system clock only used timer. */ 165#define CONFIG_SYS_CLK_FREQ 50000000 166#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 167#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 168#define CONFIG_SYS_TMU_CLK_DIV 4 169 170#endif /* __SH7785LCR_H */ 171