1/* 2 * (C) Copyright 2003 3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * File: mpc5xx.h 10 * 11 * Discription: mpc5xx specific definitions 12 * 13 */ 14 15#ifndef __MPC5XX_H__ 16#define __MPC5XX_H__ 17 18 19/*----------------------------------------------------------------------- 20 * Exception offsets (PowerPC standard) 21 */ 22#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 23#define _START_OFFSET EXC_OFF_SYS_RESET 24 25/*----------------------------------------------------------------------- 26 * ISB bit in IMMR to set internal memory map 27 */ 28 29#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1) 30 31/*----------------------------------------------------------------------- 32 * SYPCR - System Protection Control Register 33 */ 34#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */ 35#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ 36#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ 37#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ 38#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ 39#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ 40#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ 41 42/*----------------------------------------------------------------------- 43 * SIUMCR - SIU Module Configuration Register 44 */ 45#define SIUMCR_EARB 0x80000000 /* External Arbitration */ 46#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ 47#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ 48#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ 49#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ 50#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ 51#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ 52#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ 53#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ 54#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ 55#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ 56#define SIUMCR_DBGC01 0x00200000 /* - " - */ 57#define SIUMCR_DBGC10 0x00400000 /* - " - */ 58#define SIUMCR_DBGC11 0x00600000 /* - " - */ 59#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ 60#define SIUMCR_DBPC01 0x00080000 /* - " - */ 61#define SIUMCR_DBPC10 0x00100000 /* - " - */ 62#define SIUMCR_DBPC11 0x00180000 /* - " - */ 63#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ 64#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ 65#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ 66#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ 67#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ 68#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ 69#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ 70#define SIUMCR_SC10 0x00004000 /* Single adress show */ 71#define SIUMCR_SC11 0x00006000 /* Single adress */ 72#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */ 73#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ 74#define SIUMCR_MLRC01 0x00000400 /* - " - */ 75#define SIUMCR_MLRC10 0x00000800 /* - " - */ 76#define SIUMCR_MLRC11 0x00000c00 /* - " - */ 77#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ 78 79/*----------------------------------------------------------------------- 80 * TBSCR - Time Base Status and Control Register 81 */ 82#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ 83#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ 84#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */ 85 86/*----------------------------------------------------------------------- 87 * PISCR - Periodic Interrupt Status and Control Register 88 */ 89#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ 90#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ 91 92/*----------------------------------------------------------------------- 93 * PLPRCR - PLL, Low-Power, and Reset Control Register 94 */ 95#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */ 96#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ 97#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ 98#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ 99#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ 100#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ 101#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ 102#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ 103#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ 104#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ 105 106/*----------------------------------------------------------------------- 107 * SCCR - System Clock and reset Control Register 108 */ 109#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ 110#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ 111#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ 112#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ 113#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ 114#define SCCR_EBDF11 0x00060000 /* reserved */ 115#define SCCR_TBS 0x02000000 /* Time Base Source */ 116#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ 117#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ 118#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ 119#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ 120#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ 121 122/*----------------------------------------------------------------------- 123 * MC - Memory Controller 124 */ 125#define BR_V 0x00000001 /* Bank valid */ 126#define BR_BI 0x00000002 /* Burst inhibit */ 127#define BR_PS_8 0x00000400 /* 8 bit port size */ 128#define BR_PS_16 0x00000800 /* 16 bit port size */ 129#define BR_PS_32 0x00000000 /* 32 bit port size */ 130#define BR_LBDIR 0x00000008 /* Late burst data in progess */ 131#define BR_SETA 0x00000004 /* External Data Acknowledge */ 132#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ 133#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ 134#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ 135#define OR_TRLX 0x00000001 /* Timing relaxed */ 136#define OR_BSCY 0x00000060 /* Burst beats length in clocks */ 137#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ 138#define OR_CSNT 0x00000800 /* Chip-select negotation time */ 139#define OR_ETHR 0x00000100 /* Extended hold time on read */ 140#define OR_ADDR_MK_FF 0xFF000000 141#define OR_ADDR_MK_FFFF 0xFFFF0000 142 143/*----------------------------------------------------------------------- 144 * UMCR - UIMB Module Configuration Register 145 */ 146#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ 147#define UMCR_HSPEED 0x10000000 /* Half speed */ 148 149/*----------------------------------------------------------------------- 150 * ICTRL - I-Bus Support Control Register 151 */ 152#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */ 153 154 155#define NR_IRQS 0 /* Place this later in a separate file */ 156 157/*----------------------------------------------------------------------- 158 * SCI - Serial communication interface 159 */ 160 161#define SCI_TDRE 0x0100 /* Transmit data register empty */ 162#define SCI_TE 0x0008 /* Transmitter enabled */ 163#define SCI_RE 0x0004 /* Receiver enabled */ 164#define SCI_RDRF 0x0040 /* Receive data register full */ 165#define SCI_PE 0x0400 /* Parity enable */ 166#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ 167#define SCI_SCXDR_MK 0x00ff /* Data register mask */ 168#define SCI_M_11 0x0200 /* Frame size is 11 bit */ 169#define SCI_M_10 0x0000 /* Frame size is 10 bit */ 170#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ 171#define SCI_PORT_2 ((int)2) 172 173#endif /* __MPC5XX_H__ */ 174