1/* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _ASM_ARCH_HARDWARE_H 9#define _ASM_ARCH_HARDWARE_H 10 11#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 12#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 13#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 14#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 15 16#define ZYNQ_I2C_BASEADDR0 0xFF020000 17#define ZYNQ_I2C_BASEADDR1 0xFF030000 18 19#define ARASAN_NAND_BASEADDR 0xFF100000 20 21#define ZYNQMP_SATA_BASEADDR 0xFD0C0000 22 23#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 24#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 25 26#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 27#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 28 29struct crlapb_regs { 30 u32 reserved0[36]; 31 u32 cpu_r5_ctrl; /* 0x90 */ 32 u32 reserved1[37]; 33 u32 timestamp_ref_ctrl; /* 0x128 */ 34 u32 reserved2[53]; 35 u32 boot_mode; /* 0x200 */ 36 u32 reserved3[14]; 37 u32 rst_lpd_top; /* 0x23C */ 38 u32 reserved4[26]; 39}; 40 41#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 42 43#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 44#define ZYNQMP_IOU_SCNTR 0xFF250000 45#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 46#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 47 48struct iou_scntr { 49 u32 counter_control_register; 50 u32 reserved0[7]; 51 u32 base_frequency_id_register; 52}; 53 54#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) 55 56struct iou_scntr_secure { 57 u32 counter_control_register; 58 u32 reserved0[7]; 59 u32 base_frequency_id_register; 60}; 61 62#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 63 64/* Bootmode setting values */ 65#define BOOT_MODES_MASK 0x0000000F 66#define QSPI_MODE_24BIT 0x00000001 67#define QSPI_MODE_32BIT 0x00000002 68#define SD_MODE 0x00000003 /* sd 0 */ 69#define SD_MODE1 0x00000005 /* sd 1 */ 70#define NAND_MODE 0x00000004 71#define EMMC_MODE 0x00000006 72#define JTAG_MODE 0x00000000 73 74#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 75 76struct iou_slcr_regs { 77 u32 mio_pin[78]; 78 u32 reserved[442]; 79}; 80 81#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 82 83#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 84 85struct rpu_regs { 86 u32 rpu_glbl_ctrl; 87 u32 reserved0[63]; 88 u32 rpu0_cfg; /* 0x100 */ 89 u32 reserved1[63]; 90 u32 rpu1_cfg; /* 0x200 */ 91}; 92 93#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 94 95#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 96 97struct crfapb_regs { 98 u32 reserved0[65]; 99 u32 rst_fpd_apu; /* 0x104 */ 100 u32 reserved1; 101}; 102 103#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 104 105#define ZYNQMP_APU_BASEADDR 0xFD5C0000 106 107struct apu_regs { 108 u32 reserved0[16]; 109 u32 rvbar_addr0_l; /* 0x40 */ 110 u32 rvbar_addr0_h; /* 0x44 */ 111 u32 reserved1[20]; 112}; 113 114#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 115 116/* Board version value */ 117#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 118#define ZYNQMP_CSU_VERSION_SILICON 0x0 119#define ZYNQMP_CSU_VERSION_EP108 0x1 120#define ZYNQMP_CSU_VERSION_VELOCE 0x2 121#define ZYNQMP_CSU_VERSION_QEMU 0x3 122 123#define ZYNQMP_SILICON_VER_MASK 0xF000 124#define ZYNQMP_SILICON_VER_SHIFT 12 125 126struct csu_regs { 127 u32 reserved0[17]; 128 u32 version; 129}; 130 131#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 132 133#endif /* _ASM_ARCH_HARDWARE_H */ 134