1/* 2 * Copyright (C) 2009 Texas Instruments Incorporated 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6#ifndef _GPIO_DEFS_H_ 7#define _GPIO_DEFS_H_ 8 9#ifndef CONFIG_SOC_DA8XX 10#define DAVINCI_GPIO_BINTEN 0x01C67008 11#define DAVINCI_GPIO_BANK01 0x01C67010 12#define DAVINCI_GPIO_BANK23 0x01C67038 13#define DAVINCI_GPIO_BANK45 0x01C67060 14#define DAVINCI_GPIO_BANK67 0x01C67088 15 16#else /* CONFIG_SOC_DA8XX */ 17#define DAVINCI_GPIO_BINTEN 0x01E26008 18#define DAVINCI_GPIO_BANK01 0x01E26010 19#define DAVINCI_GPIO_BANK23 0x01E26038 20#define DAVINCI_GPIO_BANK45 0x01E26060 21#define DAVINCI_GPIO_BANK67 0x01E26088 22#define DAVINCI_GPIO_BANK8 0x01E260B0 23#endif /* CONFIG_SOC_DA8XX */ 24 25struct davinci_gpio { 26 unsigned int dir; 27 unsigned int out_data; 28 unsigned int set_data; 29 unsigned int clr_data; 30 unsigned int in_data; 31 unsigned int set_rising; 32 unsigned int clr_rising; 33 unsigned int set_falling; 34 unsigned int clr_falling; 35 unsigned int intstat; 36}; 37 38struct davinci_gpio_bank { 39 int num_gpio; 40 unsigned int irq_num; 41 unsigned int irq_mask; 42 unsigned long *in_use; 43 unsigned long base; 44}; 45 46#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) 47#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) 48#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) 49#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) 50#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) 51 52#define gpio_status() gpio_info() 53#define GPIO_NAME_SIZE 20 54#if defined(CONFIG_SOC_DM644X) 55/* GPIO0 to GPIO53, omit the V3.3 volts one */ 56#define MAX_NUM_GPIOS 70 57#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) 58#define MAX_NUM_GPIOS 128 59#else 60#define MAX_NUM_GPIOS 144 61#endif 62#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) 63#define GPIO_BIT(gp) ((gp) & 0x1F) 64 65void gpio_info(void); 66 67#endif 68