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7#ifndef _DV_PSC_DEFS_H_
8#define _DV_PSC_DEFS_H_
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13
14struct dv_psc_regs {
15 unsigned int pid;
16 unsigned char rsvd0[16];
17 unsigned char rsvd1[4];
18 unsigned int inteval;
19 unsigned char rsvd2[36];
20 unsigned int merrpr0;
21 unsigned int merrpr1;
22 unsigned char rsvd3[8];
23 unsigned int merrcr0;
24 unsigned int merrcr1;
25 unsigned char rsvd4[8];
26 unsigned int perrpr;
27 unsigned char rsvd5[4];
28 unsigned int perrcr;
29 unsigned char rsvd6[4];
30 unsigned int epcpr;
31 unsigned char rsvd7[4];
32 unsigned int epccr;
33 unsigned char rsvd8[144];
34 unsigned char rsvd9[20];
35 unsigned int ptcmd;
36 unsigned char rsvd10[4];
37 unsigned int ptstat;
38 unsigned char rsvd11[212];
39 unsigned int pdstat0;
40 unsigned int pdstat1;
41 unsigned char rsvd12[248];
42 unsigned int pdctl0;
43 unsigned int pdctl1;
44 unsigned char rsvd13[536];
45 unsigned int mckout0;
46 unsigned int mckout1;
47 unsigned char rsvd14[728];
48 unsigned int mdstat[52];
49 unsigned char rsvd15[304];
50 unsigned int mdctl[52];
51};
52
53
54#define EMURSTIE_MASK (0x00000200)
55
56#define PD0 (0)
57
58#define PSC_ENABLE (0x3)
59#define PSC_DISABLE (0x2)
60#define PSC_SYNCRESET (0x1)
61#define PSC_SWRSTDISABLE (0x0)
62
63#define PSC_GOSTAT (1 << 0)
64#define PSC_MD_STATE_MSK (0x1f)
65
66#define PSC_CMD_GO (1 << 0)
67
68#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
69
70#endif
71