LXR uboot/arch/x86/cpu/quark/irq.c

   1/*
   2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3 * Copyright (C) 2015 Google, Inc
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <asm/irq.h>
  11#include <asm/arch/device.h>
  12#include <asm/arch/quark.h>
  13
  14int quark_irq_router_probe(struct udevice *dev)
  15{
  16        struct quark_rcba *rcba;
  17        u32 base;
  18
  19        qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
  20        base &= ~MEM_BAR_EN;
  21        rcba = (struct quark_rcba *)base;
  22
  23        /*
  24         * Route Quark PCI device interrupt pin to PIRQ
  25         *
  26         * Route device#23's INTA/B/C/D to PIRQA/B/C/D
  27         * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
  28         */
  29        writew(PIRQC, &rcba->rmu_ir);
  30        writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
  31               &rcba->d23_ir);
  32        writew(PIRQD, &rcba->core_ir);
  33        writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
  34               &rcba->d20d21_ir);
  35
  36        return irq_router_common_init(dev);
  37}
  38
  39static const struct udevice_id quark_irq_router_ids[] = {
  40        { .compatible = "intel,quark-irq-router" },
  41        { }
  42};
  43
  44U_BOOT_DRIVER(quark_irq_router_drv) = {
  45        .name           = "quark_intel_irq",
  46        .id             = UCLASS_IRQ,
  47        .of_match       = quark_irq_router_ids,
  48        .probe          = quark_irq_router_probe,
  49};
  50