LXR uboot/board/socrates/law.c

   1/*
   2 * (C) Copyright 2008
   3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   4 *
   5 * Copyright 2008 Freescale Semiconductor, Inc.
   6 *
   7 * (C) Copyright 2000
   8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#include <common.h>
  14#include <asm/fsl_law.h>
  15#include <asm/mmu.h>
  16
  17/*
  18 * LAW(Local Access Window) configuration:
  19 *
  20 * 0x0000_0000     0x2fff_ffff     DDR                     512M
  21 * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  22 * 0xc000_0000     0xc00f_ffff     FPGA                    1M
  23 * 0xc800_0000     0xcbff_ffff     LIME                    64M
  24 * 0xe000_0000     0xe00f_ffff     CCSR                    1M (mapped by CCSRBAR)
  25 * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
  26 * 0xfc00_0000     0xffff_ffff     FLASH                   64M
  27 *
  28 * Notes:
  29 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  30 *    If flash is 8M at default position (last 8M), no LAW needed.
  31 */
  32
  33struct law_entry law_table[] = {
  34        SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
  35        SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
  36        SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  37        SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
  38#if defined(CONFIG_SYS_FPGA_BASE)
  39        SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
  40#endif
  41        SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  42};
  43
  44int num_law_entries = ARRAY_SIZE(law_table);
  45