1/* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008 Armadeus Systems, nc 4 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org> 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * (C) Copyright 2003 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 11 * This file is based on mpc4200fec.h 12 * (C) Copyright Motorola, Inc., 2000 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 18#ifndef __FEC_MXC_H 19#define __FEC_MXC_H 20 21void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 22 23/** 24 * Layout description of the FEC 25 */ 26struct ethernet_regs { 27 28/* [10:2]addr = 00 */ 29 30/* Control and status Registers (offset 000-1FF) */ 31 32 uint32_t res0[1]; /* MBAR_ETH + 0x000 */ 33 uint32_t ievent; /* MBAR_ETH + 0x004 */ 34 uint32_t imask; /* MBAR_ETH + 0x008 */ 35 36 uint32_t res1[1]; /* MBAR_ETH + 0x00C */ 37 uint32_t r_des_active; /* MBAR_ETH + 0x010 */ 38 uint32_t x_des_active; /* MBAR_ETH + 0x014 */ 39 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */ 40 uint32_t ecntrl; /* MBAR_ETH + 0x024 */ 41 42 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */ 43 uint32_t mii_data; /* MBAR_ETH + 0x040 */ 44 uint32_t mii_speed; /* MBAR_ETH + 0x044 */ 45 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */ 46 uint32_t mib_control; /* MBAR_ETH + 0x064 */ 47 48 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */ 49 uint32_t r_cntrl; /* MBAR_ETH + 0x084 */ 50 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */ 51 uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */ 52 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */ 53 uint32_t paddr1; /* MBAR_ETH + 0x0E4 */ 54 uint32_t paddr2; /* MBAR_ETH + 0x0E8 */ 55 uint32_t op_pause; /* MBAR_ETH + 0x0EC */ 56 57 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */ 58 uint32_t iaddr1; /* MBAR_ETH + 0x118 */ 59 uint32_t iaddr2; /* MBAR_ETH + 0x11C */ 60 uint32_t gaddr1; /* MBAR_ETH + 0x120 */ 61 uint32_t gaddr2; /* MBAR_ETH + 0x124 */ 62 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */ 63 64 uint32_t x_wmrk; /* MBAR_ETH + 0x144 */ 65 uint32_t res10[1]; /* MBAR_ETH + 0x148 */ 66 uint32_t r_bound; /* MBAR_ETH + 0x14C */ 67 uint32_t r_fstart; /* MBAR_ETH + 0x150 */ 68 uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */ 69 uint32_t erdsr; /* MBAR_ETH + 0x180 */ 70 uint32_t etdsr; /* MBAR_ETH + 0x184 */ 71 uint32_t emrbr; /* MBAR_ETH + 0x188 */ 72 uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ 73 74/* MIB COUNTERS (Offset 200-2FF) */ 75 76 uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ 77 uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ 78 uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ 79 uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ 80 uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */ 81 uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */ 82 uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */ 83 uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */ 84 uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */ 85 uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */ 86 uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */ 87 uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */ 88 uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */ 89 uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */ 90 uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ 91 uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ 92 uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ 93 uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */ 94 uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */ 95 uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ 96 uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */ 97 uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */ 98 uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */ 99 uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */ 100 uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */ 101 uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */ 102 uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */ 103 uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */ 104 uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */ 105 uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ 106 107 uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */ 108 uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */ 109 uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */ 110 uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ 111 uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ 112 uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */ 113 uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */ 114 uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */ 115 uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */ 116 uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */ 117 118 uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ 119 120 uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */ 121 uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ 122 uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ 123 uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ 124 uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ 125 uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ 126 uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ 127 uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */ 128 uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */ 129 uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ 130 uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */ 131 uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */ 132 uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */ 133 uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ 134 uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ 135 136 uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ 137 138#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 139 uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ 140 uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ 141 uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ 142 uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ 143 uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ 144#else 145 uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ 146#endif 147}; 148 149#define FEC_IEVENT_HBERR 0x80000000 150#define FEC_IEVENT_BABR 0x40000000 151#define FEC_IEVENT_BABT 0x20000000 152#define FEC_IEVENT_GRA 0x10000000 153#define FEC_IEVENT_TXF 0x08000000 154#define FEC_IEVENT_TXB 0x04000000 155#define FEC_IEVENT_RXF 0x02000000 156#define FEC_IEVENT_RXB 0x01000000 157#define FEC_IEVENT_MII 0x00800000 158#define FEC_IEVENT_EBERR 0x00400000 159#define FEC_IEVENT_LC 0x00200000 160#define FEC_IEVENT_RL 0x00100000 161#define FEC_IEVENT_UN 0x00080000 162 163#define FEC_IMASK_HBERR 0x80000000 164#define FEC_IMASK_BABR 0x40000000 165#define FEC_IMASKT_BABT 0x20000000 166#define FEC_IMASK_GRA 0x10000000 167#define FEC_IMASKT_TXF 0x08000000 168#define FEC_IMASK_TXB 0x04000000 169#define FEC_IMASKT_RXF 0x02000000 170#define FEC_IMASK_RXB 0x01000000 171#define FEC_IMASK_MII 0x00800000 172#define FEC_IMASK_EBERR 0x00400000 173#define FEC_IMASK_LC 0x00200000 174#define FEC_IMASKT_RL 0x00100000 175#define FEC_IMASK_UN 0x00080000 176 177 178#define FEC_RCNTRL_MAX_FL_SHIFT 16 179#define FEC_RCNTRL_LOOP 0x00000001 180#define FEC_RCNTRL_DRT 0x00000002 181#define FEC_RCNTRL_MII_MODE 0x00000004 182#define FEC_RCNTRL_PROM 0x00000008 183#define FEC_RCNTRL_BC_REJ 0x00000010 184#define FEC_RCNTRL_FCE 0x00000020 185#define FEC_RCNTRL_RGMII 0x00000040 186#define FEC_RCNTRL_RMII 0x00000100 187#define FEC_RCNTRL_RMII_10T 0x00000200 188 189#define FEC_TCNTRL_GTS 0x00000001 190#define FEC_TCNTRL_HBC 0x00000002 191#define FEC_TCNTRL_FDEN 0x00000004 192#define FEC_TCNTRL_TFC_PAUSE 0x00000008 193#define FEC_TCNTRL_RFC_PAUSE 0x00000010 194 195#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ 196#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ 197#define FEC_ECNTRL_SPEED 0x00000020 198#define FEC_ECNTRL_DBSWAP 0x00000100 199 200#define FEC_X_WMRK_STRFWD 0x00000100 201 202#define FEC_X_DES_ACTIVE_TDAR 0x01000000 203#define FEC_R_DES_ACTIVE_RDAR 0x01000000 204 205#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 206/* defines for MIIGSK */ 207/* RMII frequency control: 0=50MHz, 1=5MHz */ 208#define MIIGSK_CFGR_FRCONT (1 << 6) 209/* loopback mode */ 210#define MIIGSK_CFGR_LBMODE (1 << 4) 211/* echo mode */ 212#define MIIGSK_CFGR_EMODE (1 << 3) 213/* MII gasket mode field */ 214#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) 215/* MMI/7-Wire mode */ 216#define MIIGSK_CFGR_IF_MODE_MII (0 << 0) 217/* RMII mode */ 218#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) 219/* reflects MIIGSK Enable bit (RO) */ 220#define MIIGSK_ENR_READY (1 << 2) 221/* enable MIGSK (set by default) */ 222#define MIIGSK_ENR_EN (1 << 1) 223#endif 224 225/** 226 * @brief Receive & Transmit Buffer Descriptor definitions 227 * 228 * Note: The first BD must be aligned (see DB_ALIGNMENT) 229 */ 230struct fec_bd { 231 uint16_t data_length; /* payload's length in bytes */ 232 uint16_t status; /* BD's staus (see datasheet) */ 233 uint32_t data_pointer; /* payload's buffer address */ 234}; 235 236/** 237 * Supported phy types on this platform 238 */ 239enum xceiver_type { 240 SEVENWIRE, /* 7-wire */ 241 MII10, /* MII 10Mbps */ 242 MII100, /* MII 100Mbps */ 243 RMII, /* RMII */ 244 RGMII, /* RGMII */ 245}; 246 247/** 248 * @brief i.MX27-FEC private structure 249 */ 250struct fec_priv { 251 struct ethernet_regs *eth; /* pointer to register'S base */ 252 enum xceiver_type xcv_type; /* transceiver type */ 253 struct fec_bd *rbd_base; /* RBD ring */ 254 int rbd_index; /* next receive BD to read */ 255 struct fec_bd *tbd_base; /* TBD ring */ 256 int tbd_index; /* next transmit BD to write */ 257 bd_t *bd; 258 uint8_t *tdb_ptr; 259 int dev_id; 260 struct mii_dev *bus; 261#ifdef CONFIG_PHYLIB 262 struct phy_device *phydev; 263#else 264 int phy_id; 265 int (*mii_postcall)(int); 266#endif 267}; 268 269/** 270 * @brief Numbers of buffer descriptors for receiving 271 * 272 * The number defines the stocked memory buffers for the receiving task. 273 * Larger values makes no sense in this limited environment. 274 */ 275#define FEC_RBD_NUM 64 276 277/** 278 * @brief Define the ethernet packet size limit in memory 279 * 280 * Note: Do not shrink this number. This will force the FEC to spread larger 281 * frames in more than one BD. This is nothing to worry about, but the current 282 * driver can't handle it. 283 */ 284#define FEC_MAX_PKT_SIZE 1536 285 286/* Receive BD status bits */ 287#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */ 288#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */ 289/* Receive BD status: Buffer is last in frame (useless here!) */ 290#define FEC_RBD_LAST 0x0800 291#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */ 292/* Receive BD status: The received frame is broadcast frame */ 293#define FEC_RBD_BC 0x0080 294/* Receive BD status: The received frame is multicast frame */ 295#define FEC_RBD_MC 0x0040 296#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */ 297#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */ 298#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */ 299#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */ 300#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */ 301#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ 302 FEC_RBD_OV | FEC_RBD_TR) 303 304/* Transmit BD status bits */ 305#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */ 306#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */ 307#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */ 308#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */ 309#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */ 310 311/* MII-related definitios */ 312#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 313#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 314#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 315#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 316#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 317#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ 318#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 319 320#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 321#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 322 323#endif /* __FEC_MXC_H */ 324