LXR uboot/drivers/serial/serial

   1/*
   2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <dm.h>
   9#include <errno.h>
  10#include <watchdog.h>
  11#include <asm/arch/imx-regs.h>
  12#include <asm/arch/clock.h>
  13#include <dm/platform_data/serial_mxc.h>
  14#include <serial.h>
  15#include <linux/compiler.h>
  16
  17/* UART Control Register Bit Fields.*/
  18#define  URXD_CHARRDY    (1<<15)
  19#define  URXD_ERR        (1<<14)
  20#define  URXD_OVRRUN     (1<<13)
  21#define  URXD_FRMERR     (1<<12)
  22#define  URXD_BRK        (1<<11)
  23#define  URXD_PRERR      (1<<10)
  24#define  URXD_RX_DATA    (0xFF)
  25#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
  26#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  27#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  28#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  29#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  30#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  31#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
  32#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  33#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  34#define  UCR1_SNDBRK     (1<<4)  /* Send break */
  35#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  36#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
  37#define  UCR1_DOZE       (1<<1)  /* Doze */
  38#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
  39#define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  40#define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  41#define  UCR2_CTSC       (1<<13) /* CTS pin control */
  42#define  UCR2_CTS        (1<<12) /* Clear to send */
  43#define  UCR2_ESCEN      (1<<11) /* Escape enable */
  44#define  UCR2_PREN       (1<<8)  /* Parity enable */
  45#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
  46#define  UCR2_STPB       (1<<6)  /* Stop */
  47#define  UCR2_WS         (1<<5)  /* Word size */
  48#define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  49#define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  50#define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
  51#define  UCR2_SRST       (1<<0)  /* SW reset */
  52#define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
  53#define  UCR3_PARERREN   (1<<12) /* Parity enable */
  54#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
  55#define  UCR3_DSR        (1<<10) /* Data set ready */
  56#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
  57#define  UCR3_RI         (1<<8)  /* Ring indicator */
  58#define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
  59#define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
  60#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
  61#define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
  62#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
  63#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
  64#define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
  65#define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
  66#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
  67#define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
  68#define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
  69#define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
  70#define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
  71#define  UCR4_IRSC       (1<<5)  /* IR special case */
  72#define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
  73#define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
  74#define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
  75#define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
  76#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
  77#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
  78#define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
  79#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
  80#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
  81#define  USR1_RTSS       (1<<14) /* RTS pin status */
  82#define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
  83#define  USR1_RTSD       (1<<12) /* RTS delta */
  84#define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
  85#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
  86#define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
  87#define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
  88#define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
  89#define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
  90#define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
  91#define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
  92#define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
  93#define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
  94#define  USR2_IDLE       (1<<12) /* Idle condition */
  95#define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
  96#define  USR2_WAKE       (1<<7)  /* Wake */
  97#define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
  98#define  USR2_TXDC       (1<<3)  /* Transmitter complete */
  99#define  USR2_BRCD       (1<<2)  /* Break condition */
 100#define  USR2_ORE        (1<<1)  /* Overrun error */
 101#define  USR2_RDR        (1<<0)  /* Recv data ready */
 102#define  UTS_FRCPERR     (1<<13) /* Force parity error */
 103#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
 104#define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
 105#define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
 106#define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
 107#define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
 108#define  UTS_SOFTRST     (1<<0)  /* Software reset */
 109
 110#ifndef CONFIG_DM_SERIAL
 111
 112#ifndef CONFIG_MXC_UART_BASE
 113#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
 114#endif
 115
 116#define UART_PHYS       CONFIG_MXC_UART_BASE
 117
 118#define __REG(x)     (*((volatile u32 *)(x)))
 119
 120/* Register definitions */
 121#define URXD  0x0  /* Receiver Register */
 122#define UTXD  0x40 /* Transmitter Register */
 123#define UCR1  0x80 /* Control Register 1 */
 124#define UCR2  0x84 /* Control Register 2 */
 125#define UCR3  0x88 /* Control Register 3 */
 126#define UCR4  0x8c /* Control Register 4 */
 127#define UFCR  0x90 /* FIFO Control Register */
 128#define USR1  0x94 /* Status Register 1 */
 129#define USR2  0x98 /* Status Register 2 */
 130#define UESC  0x9c /* Escape Character Register */
 131#define UTIM  0xa0 /* Escape Timer Register */
 132#define UBIR  0xa4 /* BRM Incremental Register */
 133#define UBMR  0xa8 /* BRM Modulator Register */
 134#define UBRC  0xac /* Baud Rate Count Register */
 135#define UTS   0xb4 /* UART Test Register (mx31) */
 136
 137DECLARE_GLOBAL_DATA_PTR;
 138
 139#define TXTL  2 /* reset default */
 140#define RXTL  1 /* reset default */
 141#define RFDIV 4 /* divide input clock by 2 */
 142
 143static void mxc_serial_setbrg(void)
 144{
 145        u32 clk = imx_get_uartclk();
 146
 147        if (!gd->baudrate)
 148                gd->baudrate = CONFIG_BAUDRATE;
 149
 150        __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
 151                | (TXTL << UFCR_TXTL_SHF)
 152                | (RXTL << UFCR_RXTL_SHF);
 153        __REG(UART_PHYS + UBIR) = 0xf;
 154        __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
 155
 156}
 157
 158static int mxc_serial_getc(void)
 159{
 160        while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
 161                WATCHDOG_RESET();
 162        return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
 163}
 164
 165static void mxc_serial_putc(const char c)
 166{
 167        __REG(UART_PHYS + UTXD) = c;
 168
 169        /* wait for transmitter to be ready */
 170        while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
 171                WATCHDOG_RESET();
 172
 173        /* If \n, also do \r */
 174        if (c == '\n')
 175                serial_putc ('\r');
 176}
 177
 178/*
 179 * Test whether a character is in the RX buffer
 180 */
 181static int mxc_serial_tstc(void)
 182{
 183        /* If receive fifo is empty, return false */
 184        if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
 185                return 0;
 186        return 1;
 187}
 188
 189/*
 190 * Initialise the serial port with the given baudrate. The settings
 191 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 192 *
 193 */
 194static int mxc_serial_init(void)
 195{
 196        __REG(UART_PHYS + UCR1) = 0x0;
 197        __REG(UART_PHYS + UCR2) = 0x0;
 198
 199        while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
 200
 201        __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
 202        __REG(UART_PHYS + UCR4) = 0x8000;
 203        __REG(UART_PHYS + UESC) = 0x002b;
 204        __REG(UART_PHYS + UTIM) = 0x0;
 205
 206        __REG(UART_PHYS + UTS) = 0x0;
 207
 208        serial_setbrg();
 209
 210        __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
 211
 212        __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
 213
 214        return 0;
 215}
 216
 217static struct serial_device mxc_serial_drv = {
 218        .name   = "mxc_serial",
 219        .start  = mxc_serial_init,
 220        .stop   = NULL,
 221        .setbrg = mxc_serial_setbrg,
 222        .putc   = mxc_serial_putc,
 223        .puts   = default_serial_puts,
 224        .getc   = mxc_serial_getc,
 225        .tstc   = mxc_serial_tstc,
 226};
 227
 228void mxc_serial_initialize(void)
 229{
 230        serial_register(&mxc_serial_drv);
 231}
 232
 233__weak struct serial_device *default_serial_console(void)
 234{
 235        return &mxc_serial_drv;
 236}
 237#endif
 238
 239#ifdef CONFIG_DM_SERIAL
 240
 241struct mxc_uart {
 242        u32 rxd;
 243        u32 spare0[15];
 244
 245        u32 txd;
 246        u32 spare1[15];
 247
 248        u32 cr1;
 249        u32 cr2;
 250        u32 cr3;
 251        u32 cr4;
 252
 253        u32 fcr;
 254        u32 sr1;
 255        u32 sr2;
 256        u32 esc;
 257
 258        u32 tim;
 259        u32 bir;
 260        u32 bmr;
 261        u32 brc;
 262
 263        u32 onems;
 264        u32 ts;
 265};
 266
 267int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 268{
 269        struct mxc_serial_platdata *plat = dev->platdata;
 270        struct mxc_uart *const uart = plat->reg;
 271        u32 clk = imx_get_uartclk();
 272
 273        writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
 274        writel(0xf, &uart->bir);
 275        writel(clk / (2 * baudrate), &uart->bmr);
 276
 277        writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
 278               &uart->cr2);
 279        writel(UCR1_UARTEN, &uart->cr1);
 280
 281        return 0;
 282}
 283
 284static int mxc_serial_probe(struct udevice *dev)
 285{
 286        struct mxc_serial_platdata *plat = dev->platdata;
 287        struct mxc_uart *const uart = plat->reg;
 288
 289        writel(0, &uart->cr1);
 290        writel(0, &uart->cr2);
 291        while (!(readl(&uart->cr2) & UCR2_SRST));
 292        writel(0x704 | UCR3_ADNIMP, &uart->cr3);
 293        writel(0x8000, &uart->cr4);
 294        writel(0x2b, &uart->esc);
 295        writel(0, &uart->tim);
 296        writel(0, &uart->ts);
 297
 298        return 0;
 299}
 300
 301static int mxc_serial_getc(struct udevice *dev)
 302{
 303        struct mxc_serial_platdata *plat = dev->platdata;
 304        struct mxc_uart *const uart = plat->reg;
 305
 306        if (readl(&uart->ts) & UTS_RXEMPTY)
 307                return -EAGAIN;
 308
 309        return readl(&uart->rxd) & URXD_RX_DATA;
 310}
 311
 312static int mxc_serial_putc(struct udevice *dev, const char ch)
 313{
 314        struct mxc_serial_platdata *plat = dev->platdata;
 315        struct mxc_uart *const uart = plat->reg;
 316
 317        if (!(readl(&uart->ts) & UTS_TXEMPTY))
 318                return -EAGAIN;
 319
 320        writel(ch, &uart->txd);
 321
 322        return 0;
 323}
 324
 325static int mxc_serial_pending(struct udevice *dev, bool input)
 326{
 327        struct mxc_serial_platdata *plat = dev->platdata;
 328        struct mxc_uart *const uart = plat->reg;
 329        uint32_t sr2 = readl(&uart->sr2);
 330
 331        if (input)
 332                return sr2 & USR2_RDR ? 1 : 0;
 333        else
 334                return sr2 & USR2_TXDC ? 0 : 1;
 335}
 336
 337static const struct dm_serial_ops mxc_serial_ops = {
 338        .putc = mxc_serial_putc,
 339        .pending = mxc_serial_pending,
 340        .getc = mxc_serial_getc,
 341        .setbrg = mxc_serial_setbrg,
 342};
 343
 344U_BOOT_DRIVER(serial_mxc) = {
 345        .name   = "serial_mxc",
 346        .id     = UCLASS_SERIAL,
 347        .probe = mxc_serial_probe,
 348        .ops    = &mxc_serial_ops,
 349        .flags = DM_FLAG_PRE_RELOC,
 350};
 351#endif
 352