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7#include <common.h>
8#include <malloc.h>
9#include <spi.h>
10#include <asm/errno.h>
11#include <asm/io.h>
12#include <asm/gpio.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/clock.h>
15#include <asm/imx-common/spi.h>
16
17#ifdef CONFIG_MX27
18
19
20
21#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
22"See linux mxc_spi driver from Freescale for details."
23#endif
24
25static unsigned long spi_bases[] = {
26 MXC_SPI_BASE_ADDRESSES
27};
28
29__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
30{
31 return -1;
32}
33
34#define OUT MXC_GPIO_DIRECTION_OUT
35
36#define reg_read readl
37#define reg_write(a, v) writel(v, a)
38
39#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
40#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100)
41#endif
42
43struct mxc_spi_slave {
44 struct spi_slave slave;
45 unsigned long base;
46 u32 ctrl_reg;
47#if defined(MXC_ECSPI)
48 u32 cfg_reg;
49#endif
50 int gpio;
51 int ss_pol;
52 unsigned int max_hz;
53 unsigned int mode;
54};
55
56static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
57{
58 return container_of(slave, struct mxc_spi_slave, slave);
59}
60
61void spi_cs_activate(struct spi_slave *slave)
62{
63 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
64 if (mxcs->gpio > 0)
65 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
66}
67
68void spi_cs_deactivate(struct spi_slave *slave)
69{
70 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
71 if (mxcs->gpio > 0)
72 gpio_set_value(mxcs->gpio,
73 !(mxcs->ss_pol));
74}
75
76u32 get_cspi_div(u32 div)
77{
78 int i;
79
80 for (i = 0; i < 8; i++) {
81 if (div <= (4 << i))
82 return i;
83 }
84 return i;
85}
86
87#ifdef MXC_CSPI
88static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
89{
90 unsigned int ctrl_reg;
91 u32 clk_src;
92 u32 div;
93 unsigned int max_hz = mxcs->max_hz;
94 unsigned int mode = mxcs->mode;
95
96 clk_src = mxc_get_clock(MXC_CSPI_CLK);
97
98 div = DIV_ROUND_UP(clk_src, max_hz);
99 div = get_cspi_div(div);
100
101 debug("clk %d Hz, div %d, real clk %d Hz\n",
102 max_hz, div, clk_src / (4 << div));
103
104 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
105 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
106 MXC_CSPICTRL_DATARATE(div) |
107 MXC_CSPICTRL_EN |
108#ifdef CONFIG_MX35
109 MXC_CSPICTRL_SSCTL |
110#endif
111 MXC_CSPICTRL_MODE;
112
113 if (mode & SPI_CPHA)
114 ctrl_reg |= MXC_CSPICTRL_PHA;
115 if (mode & SPI_CPOL)
116 ctrl_reg |= MXC_CSPICTRL_POL;
117 if (mode & SPI_CS_HIGH)
118 ctrl_reg |= MXC_CSPICTRL_SSPOL;
119 mxcs->ctrl_reg = ctrl_reg;
120
121 return 0;
122}
123#endif
124
125#ifdef MXC_ECSPI
126static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
127{
128 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
129 s32 reg_ctrl, reg_config;
130 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
131 u32 pre_div = 0, post_div = 0;
132 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
133 unsigned int max_hz = mxcs->max_hz;
134 unsigned int mode = mxcs->mode;
135
136
137
138
139
140
141 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
142 reg_write(®s->ctrl, reg_ctrl);
143 reg_ctrl |= MXC_CSPICTRL_EN;
144 reg_write(®s->ctrl, reg_ctrl);
145
146 if (clk_src > max_hz) {
147 pre_div = (clk_src - 1) / max_hz;
148
149 post_div = fls(pre_div);
150 if (post_div > 4) {
151 post_div -= 4;
152 if (post_div >= 16) {
153 printf("Error: no divider for the freq: %d\n",
154 max_hz);
155 return -1;
156 }
157 pre_div >>= post_div;
158 } else {
159 post_div = 0;
160 }
161 }
162
163 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
164 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
165 MXC_CSPICTRL_SELCHAN(cs);
166 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
167 MXC_CSPICTRL_PREDIV(pre_div);
168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
169 MXC_CSPICTRL_POSTDIV(post_div);
170
171 if (mode & SPI_CS_HIGH)
172 ss_pol = 1;
173
174 if (mode & SPI_CPOL) {
175 sclkpol = 1;
176 sclkctl = 1;
177 }
178
179 if (mode & SPI_CPHA)
180 sclkpha = 1;
181
182 reg_config = reg_read(®s->cfg);
183
184
185
186
187
188 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
189 (ss_pol << (cs + MXC_CSPICON_SSPOL));
190 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
191 (sclkpol << (cs + MXC_CSPICON_POL));
192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
193 (sclkctl << (cs + MXC_CSPICON_CTL));
194 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
195 (sclkpha << (cs + MXC_CSPICON_PHA));
196
197 debug("reg_ctrl = 0x%x\n", reg_ctrl);
198 reg_write(®s->ctrl, reg_ctrl);
199 debug("reg_config = 0x%x\n", reg_config);
200 reg_write(®s->cfg, reg_config);
201
202
203 mxcs->ctrl_reg = reg_ctrl;
204 mxcs->cfg_reg = reg_config;
205
206
207 reg_write(®s->intr, 0);
208 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
209
210 return 0;
211}
212#endif
213
214int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
215 const u8 *dout, u8 *din, unsigned long flags)
216{
217 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
218 int nbytes = DIV_ROUND_UP(bitlen, 8);
219 u32 data, cnt, i;
220 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
221 u32 ts;
222 int status;
223
224 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
225 __func__, bitlen, (u32)dout, (u32)din);
226
227 mxcs->ctrl_reg = (mxcs->ctrl_reg &
228 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
229 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
230
231 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
232#ifdef MXC_ECSPI
233 reg_write(®s->cfg, mxcs->cfg_reg);
234#endif
235
236
237 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
238
239
240
241
242
243
244 if (bitlen % 32) {
245 data = 0;
246 cnt = (bitlen % 32) / 8;
247 if (dout) {
248 for (i = 0; i < cnt; i++) {
249 data = (data << 8) | (*dout++ & 0xFF);
250 }
251 }
252 debug("Sending SPI 0x%x\n", data);
253
254 reg_write(®s->txdata, data);
255 nbytes -= cnt;
256 }
257
258 data = 0;
259
260 while (nbytes > 0) {
261 data = 0;
262 if (dout) {
263
264 if ((unsigned long)dout & 0x03) {
265 data = 0;
266 for (i = 0; i < 4; i++)
267 data = (data << 8) | (*dout++ & 0xFF);
268 } else {
269 data = *(u32 *)dout;
270 data = cpu_to_be32(data);
271 dout += 4;
272 }
273 }
274 debug("Sending SPI 0x%x\n", data);
275 reg_write(®s->txdata, data);
276 nbytes -= 4;
277 }
278
279
280 reg_write(®s->ctrl, mxcs->ctrl_reg |
281 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
282
283 ts = get_timer(0);
284 status = reg_read(®s->stat);
285
286 while ((status & MXC_CSPICTRL_TC) == 0) {
287 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
288 printf("spi_xchg_single: Timeout!\n");
289 return -1;
290 }
291 status = reg_read(®s->stat);
292 }
293
294
295 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
296
297 nbytes = DIV_ROUND_UP(bitlen, 8);
298
299 cnt = nbytes % 32;
300
301 if (bitlen % 32) {
302 data = reg_read(®s->rxdata);
303 cnt = (bitlen % 32) / 8;
304 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
305 debug("SPI Rx unaligned: 0x%x\n", data);
306 if (din) {
307 memcpy(din, &data, cnt);
308 din += cnt;
309 }
310 nbytes -= cnt;
311 }
312
313 while (nbytes > 0) {
314 u32 tmp;
315 tmp = reg_read(®s->rxdata);
316 data = cpu_to_be32(tmp);
317 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
318 cnt = min_t(u32, nbytes, sizeof(data));
319 if (din) {
320 memcpy(din, &data, cnt);
321 din += cnt;
322 }
323 nbytes -= cnt;
324 }
325
326 return 0;
327
328}
329
330int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
331 void *din, unsigned long flags)
332{
333 int n_bytes = DIV_ROUND_UP(bitlen, 8);
334 int n_bits;
335 int ret;
336 u32 blk_size;
337 u8 *p_outbuf = (u8 *)dout;
338 u8 *p_inbuf = (u8 *)din;
339
340 if (!slave)
341 return -1;
342
343 if (flags & SPI_XFER_BEGIN)
344 spi_cs_activate(slave);
345
346 while (n_bytes > 0) {
347 if (n_bytes < MAX_SPI_BYTES)
348 blk_size = n_bytes;
349 else
350 blk_size = MAX_SPI_BYTES;
351
352 n_bits = blk_size * 8;
353
354 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
355
356 if (ret)
357 return ret;
358 if (dout)
359 p_outbuf += blk_size;
360 if (din)
361 p_inbuf += blk_size;
362 n_bytes -= blk_size;
363 }
364
365 if (flags & SPI_XFER_END) {
366 spi_cs_deactivate(slave);
367 }
368
369 return 0;
370}
371
372void spi_init(void)
373{
374}
375
376
377
378
379
380
381
382
383
384static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
385 unsigned int bus, unsigned int cs)
386{
387 int ret;
388
389 mxcs->gpio = board_spi_cs_gpio(bus, cs);
390 if (mxcs->gpio == -1)
391 return 0;
392
393 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
394 if (ret) {
395 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
396 return -EINVAL;
397 }
398
399 return 0;
400}
401
402struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
403 unsigned int max_hz, unsigned int mode)
404{
405 struct mxc_spi_slave *mxcs;
406 int ret;
407
408 if (bus >= ARRAY_SIZE(spi_bases))
409 return NULL;
410
411 if (max_hz == 0) {
412 printf("Error: desired clock is 0\n");
413 return NULL;
414 }
415
416 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
417 if (!mxcs) {
418 puts("mxc_spi: SPI Slave not allocated !\n");
419 return NULL;
420 }
421
422 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
423
424 ret = setup_cs_gpio(mxcs, bus, cs);
425 if (ret < 0) {
426 free(mxcs);
427 return NULL;
428 }
429
430 mxcs->base = spi_bases[bus];
431 mxcs->max_hz = max_hz;
432 mxcs->mode = mode;
433
434 return &mxcs->slave;
435}
436
437void spi_free_slave(struct spi_slave *slave)
438{
439 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
440
441 free(mxcs);
442}
443
444int spi_claim_bus(struct spi_slave *slave)
445{
446 int ret;
447 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
448 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
449
450 reg_write(®s->rxdata, 1);
451 udelay(1);
452 ret = spi_cfg_mxc(mxcs, slave->cs);
453 if (ret) {
454 printf("mxc_spi: cannot setup SPI controller\n");
455 return ret;
456 }
457 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
458 reg_write(®s->intr, 0);
459
460 return 0;
461}
462
463void spi_release_bus(struct spi_slave *slave)
464{
465
466}
467