1/* 2 * URB OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * usb-ohci.h 8 */ 9 10/* 11 * e.g. PCI controllers need this 12 */ 13#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS 14# define ohci_readl(a) __swap_32(*((volatile u32 *)(a))) 15# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) 16#else 17# define ohci_readl(a) (*((volatile u32 *)(a))) 18# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) 19#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ 20 21#if ARCH_DMA_MINALIGN > 16 22#define ED_ALIGNMENT ARCH_DMA_MINALIGN 23#else 24#define ED_ALIGNMENT 16 25#endif 26 27#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32 28#define TD_ALIGNMENT ARCH_DMA_MINALIGN 29#else 30#define TD_ALIGNMENT 32 31#endif 32 33/* functions for doing board or CPU specific setup/cleanup */ 34int usb_board_stop(void); 35 36int usb_cpu_init(void); 37int usb_cpu_stop(void); 38int usb_cpu_init_fail(void); 39 40/* ED States */ 41#define ED_NEW 0x00 42#define ED_UNLINK 0x01 43#define ED_OPER 0x02 44#define ED_DEL 0x04 45#define ED_URB_DEL 0x08 46 47/* usb_ohci_ed */ 48struct ed { 49 __u32 hwINFO; 50 __u32 hwTailP; 51 __u32 hwHeadP; 52 __u32 hwNextED; 53 54 struct ed *ed_prev; 55 __u8 int_period; 56 __u8 int_branch; 57 __u8 int_load; 58 __u8 int_interval; 59 __u8 state; 60 __u8 type; 61 __u16 last_iso; 62 struct ed *ed_rm_list; 63 64 struct usb_device *usb_dev; 65 void *purb; 66 __u32 unused[2]; 67} __attribute__((aligned(ED_ALIGNMENT))); 68typedef struct ed ed_t; 69 70 71/* TD info field */ 72#define TD_CC 0xf0000000 73#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) 74#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) 75#define TD_EC 0x0C000000 76#define TD_T 0x03000000 77#define TD_T_DATA0 0x02000000 78#define TD_T_DATA1 0x03000000 79#define TD_T_TOGGLE 0x00000000 80#define TD_R 0x00040000 81#define TD_DI 0x00E00000 82#define TD_DI_SET(X) (((X) & 0x07)<< 21) 83#define TD_DP 0x00180000 84#define TD_DP_SETUP 0x00000000 85#define TD_DP_IN 0x00100000 86#define TD_DP_OUT 0x00080000 87 88#define TD_ISO 0x00010000 89#define TD_DEL 0x00020000 90 91/* CC Codes */ 92#define TD_CC_NOERROR 0x00 93#define TD_CC_CRC 0x01 94#define TD_CC_BITSTUFFING 0x02 95#define TD_CC_DATATOGGLEM 0x03 96#define TD_CC_STALL 0x04 97#define TD_DEVNOTRESP 0x05 98#define TD_PIDCHECKFAIL 0x06 99#define TD_UNEXPECTEDPID 0x07 100#define TD_DATAOVERRUN 0x08 101#define TD_DATAUNDERRUN 0x09 102#define TD_BUFFEROVERRUN 0x0C 103#define TD_BUFFERUNDERRUN 0x0D 104#define TD_NOTACCESSED 0x0F 105 106 107#define MAXPSW 1 108 109struct td { 110 __u32 hwINFO; 111 __u32 hwCBP; /* Current Buffer Pointer */ 112 __u32 hwNextTD; /* Next TD Pointer */ 113 __u32 hwBE; /* Memory Buffer End Pointer */ 114 115/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */ 116 __u16 hwPSW[MAXPSW]; 117/* #endif */ 118 __u8 unused; 119 __u8 index; 120 struct ed *ed; 121 struct td *next_dl_td; 122 struct usb_device *usb_dev; 123 int transfer_len; 124 __u32 data; 125 126 __u32 unused2[2]; 127} __attribute__((aligned(TD_ALIGNMENT))); 128typedef struct td td_t; 129 130#define OHCI_ED_SKIP (1 << 14) 131 132/* 133 * The HCCA (Host Controller Communications Area) is a 256 byte 134 * structure defined in the OHCI spec. that the host controller is 135 * told the base address of. It must be 256-byte aligned. 136 */ 137 138#define NUM_INTS 32 /* part of the OHCI standard */ 139struct ohci_hcca { 140 __u32 int_table[NUM_INTS]; /* Interrupt ED table */ 141#if defined(CONFIG_MPC5200) 142 __u16 pad1; /* set to 0 on each frame_no change */ 143 __u16 frame_no; /* current frame number */ 144#else 145 __u16 frame_no; /* current frame number */ 146 __u16 pad1; /* set to 0 on each frame_no change */ 147#endif 148 __u32 done_head; /* info returned for an interrupt */ 149 u8 reserved_for_hc[116]; 150} __attribute__((aligned(256))); 151 152 153/* 154 * Maximum number of root hub ports. 155 */ 156#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 157# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" 158#endif 159 160/* 161 * This is the structure of the OHCI controller's memory mapped I/O 162 * region. This is Memory Mapped I/O. You must use the ohci_readl() and 163 * ohci_writel() macros defined in this file to access these!! 164 */ 165struct ohci_regs { 166 /* control and status registers */ 167 __u32 revision; 168 __u32 control; 169 __u32 cmdstatus; 170 __u32 intrstatus; 171 __u32 intrenable; 172 __u32 intrdisable; 173 /* memory pointers */ 174 __u32 hcca; 175 __u32 ed_periodcurrent; 176 __u32 ed_controlhead; 177 __u32 ed_controlcurrent; 178 __u32 ed_bulkhead; 179 __u32 ed_bulkcurrent; 180 __u32 donehead; 181 /* frame counters */ 182 __u32 fminterval; 183 __u32 fmremaining; 184 __u32 fmnumber; 185 __u32 periodicstart; 186 __u32 lsthresh; 187 /* Root hub ports */ 188 struct ohci_roothub_regs { 189 __u32 a; 190 __u32 b; 191 __u32 status; 192 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; 193 } roothub; 194} __attribute__((aligned(32))); 195 196/* Some EHCI controls */ 197#define EHCI_USBCMD_OFF 0x20 198#define EHCI_USBCMD_HCRESET (1 << 1) 199 200/* OHCI CONTROL AND STATUS REGISTER MASKS */ 201 202/* 203 * HcControl (control) register masks 204 */ 205#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 206#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ 207#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ 208#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 209#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ 210#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 211#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 212#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 213#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 214 215/* pre-shifted values for HCFS */ 216# define OHCI_USB_RESET (0 << 6) 217# define OHCI_USB_RESUME (1 << 6) 218# define OHCI_USB_OPER (2 << 6) 219# define OHCI_USB_SUSPEND (3 << 6) 220 221/* 222 * HcCommandStatus (cmdstatus) register masks 223 */ 224#define OHCI_HCR (1 << 0) /* host controller reset */ 225#define OHCI_CLF (1 << 1) /* control list filled */ 226#define OHCI_BLF (1 << 2) /* bulk list filled */ 227#define OHCI_OCR (1 << 3) /* ownership change request */ 228#define OHCI_SOC (3 << 16) /* scheduling overrun count */ 229 230/* 231 * masks used with interrupt registers: 232 * HcInterruptStatus (intrstatus) 233 * HcInterruptEnable (intrenable) 234 * HcInterruptDisable (intrdisable) 235 */ 236#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 237#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 238#define OHCI_INTR_SF (1 << 2) /* start frame */ 239#define OHCI_INTR_RD (1 << 3) /* resume detect */ 240#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 241#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 242#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 243#define OHCI_INTR_OC (1 << 30) /* ownership change */ 244#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 245 246 247/* Virtual Root HUB */ 248struct virt_root_hub { 249 int devnum; /* Address of Root Hub endpoint */ 250 void *dev; /* was urb */ 251 void *int_addr; 252 int send; 253 int interval; 254}; 255 256/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ 257 258/* destination of request */ 259#define RH_INTERFACE 0x01 260#define RH_ENDPOINT 0x02 261#define RH_OTHER 0x03 262 263#define RH_CLASS 0x20 264#define RH_VENDOR 0x40 265 266/* Requests: bRequest << 8 | bmRequestType */ 267#define RH_GET_STATUS 0x0080 268#define RH_CLEAR_FEATURE 0x0100 269#define RH_SET_FEATURE 0x0300 270#define RH_SET_ADDRESS 0x0500 271#define RH_GET_DESCRIPTOR 0x0680 272#define RH_SET_DESCRIPTOR 0x0700 273#define RH_GET_CONFIGURATION 0x0880 274#define RH_SET_CONFIGURATION 0x0900 275#define RH_GET_STATE 0x0280 276#define RH_GET_INTERFACE 0x0A80 277#define RH_SET_INTERFACE 0x0B00 278#define RH_SYNC_FRAME 0x0C80 279/* Our Vendor Specific Request */ 280#define RH_SET_EP 0x2000 281 282 283/* Hub port features */ 284#define RH_PORT_CONNECTION 0x00 285#define RH_PORT_ENABLE 0x01 286#define RH_PORT_SUSPEND 0x02 287#define RH_PORT_OVER_CURRENT 0x03 288#define RH_PORT_RESET 0x04 289#define RH_PORT_POWER 0x08 290#define RH_PORT_LOW_SPEED 0x09 291 292#define RH_C_PORT_CONNECTION 0x10 293#define RH_C_PORT_ENABLE 0x11 294#define RH_C_PORT_SUSPEND 0x12 295#define RH_C_PORT_OVER_CURRENT 0x13 296#define RH_C_PORT_RESET 0x14 297 298/* Hub features */ 299#define RH_C_HUB_LOCAL_POWER 0x00 300#define RH_C_HUB_OVER_CURRENT 0x01 301 302#define RH_DEVICE_REMOTE_WAKEUP 0x00 303#define RH_ENDPOINT_STALL 0x01 304 305#define RH_ACK 0x01 306#define RH_REQ_ERR -1 307#define RH_NACK 0x00 308 309 310/* OHCI ROOT HUB REGISTER MASKS */ 311 312/* roothub.portstatus [i] bits */ 313#define RH_PS_CCS 0x00000001 /* current connect status */ 314#define RH_PS_PES 0x00000002 /* port enable status*/ 315#define RH_PS_PSS 0x00000004 /* port suspend status */ 316#define RH_PS_POCI 0x00000008 /* port over current indicator */ 317#define RH_PS_PRS 0x00000010 /* port reset status */ 318#define RH_PS_PPS 0x00000100 /* port power status */ 319#define RH_PS_LSDA 0x00000200 /* low speed device attached */ 320#define RH_PS_CSC 0x00010000 /* connect status change */ 321#define RH_PS_PESC 0x00020000 /* port enable status change */ 322#define RH_PS_PSSC 0x00040000 /* port suspend status change */ 323#define RH_PS_OCIC 0x00080000 /* over current indicator change */ 324#define RH_PS_PRSC 0x00100000 /* port reset status change */ 325 326/* roothub.status bits */ 327#define RH_HS_LPS 0x00000001 /* local power status */ 328#define RH_HS_OCI 0x00000002 /* over current indicator */ 329#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 330#define RH_HS_LPSC 0x00010000 /* local power status change */ 331#define RH_HS_OCIC 0x00020000 /* over current indicator change */ 332#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 333 334/* roothub.b masks */ 335#define RH_B_DR 0x0000ffff /* device removable flags */ 336#define RH_B_PPCM 0xffff0000 /* port power control mask */ 337 338/* roothub.a masks */ 339#define RH_A_NDP (0xff << 0) /* number of downstream ports */ 340#define RH_A_PSM (1 << 8) /* power switching mode */ 341#define RH_A_NPS (1 << 9) /* no power switching */ 342#define RH_A_DT (1 << 10) /* device type (mbz) */ 343#define RH_A_OCPM (1 << 11) /* over current protection mode */ 344#define RH_A_NOCP (1 << 12) /* no over current protection */ 345#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 346 347/* urb */ 348#define N_URB_TD 48 349typedef struct 350{ 351 ed_t *ed; 352 __u16 length; /* number of tds associated with this request */ 353 __u16 td_cnt; /* number of tds already serviced */ 354 struct usb_device *dev; 355 int state; 356 unsigned long pipe; 357 void *transfer_buffer; 358 int transfer_buffer_length; 359 int interval; 360 int actual_length; 361 int finished; 362 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ 363} urb_priv_t; 364#define URB_DEL 1 365 366#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ 367 368#define NUM_TD 64 /* we need more TDs than EDs */ 369 370#define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */ 371 372typedef struct ohci_device { 373 ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT); 374 td_t tds[NUM_TD] __aligned(TD_ALIGNMENT); 375 int ed_cnt; 376 int devnum; 377} ohci_dev_t; 378 379/* 380 * This is the full ohci controller description 381 * 382 * Note how the "proper" USB information is just 383 * a subset of what the full implementation needs. (Linus) 384 */ 385 386 387typedef struct ohci { 388 /* this allocates EDs for all possible endpoints */ 389 struct ohci_device ohci_dev __aligned(TD_ALIGNMENT); 390 struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT); 391 struct ohci_hcca *hcca; /* hcca */ 392 /*dma_addr_t hcca_dma;*/ 393 394 int irq; 395 int disabled; /* e.g. got a UE, we're hung */ 396 int sleeping; 397 unsigned long flags; /* for HC bugs */ 398 399 struct ohci_regs *regs; /* OHCI controller's memory */ 400 401 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ 402 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ 403 ed_t *ed_bulktail; /* last endpoint of bulk list */ 404 ed_t *ed_controltail; /* last endpoint of control list */ 405 int intrstatus; 406 __u32 hc_control; /* copy of the hc control reg */ 407 struct usb_device *dev[32]; 408 struct virt_root_hub rh; 409 410 const char *slot_name; 411} ohci_t; 412 413#ifdef CONFIG_DM_USB 414extern struct dm_usb_ops ohci_usb_ops; 415 416int ohci_register(struct udevice *dev, struct ohci_regs *regs); 417int ohci_deregister(struct udevice *dev); 418#endif 419