1/* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef _M5208EVBE_H 11#define _M5208EVBE_H 12 13/* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17#define CONFIG_MCFUART 18#define CONFIG_SYS_UART_PORT (0) 19#define CONFIG_BAUDRATE 115200 20 21#undef CONFIG_WATCHDOG 22#define CONFIG_WATCHDOG_TIMEOUT 5000 23 24/* Command line configuration */ 25#define CONFIG_CMD_CACHE 26#undef CONFIG_CMD_I2C 27#define CONFIG_CMD_MII 28#define CONFIG_CMD_PING 29#define CONFIG_CMD_REGINFO 30 31#define CONFIG_MCFFEC 32#ifdef CONFIG_MCFFEC 33# define CONFIG_MII 1 34# define CONFIG_MII_INIT 1 35# define CONFIG_SYS_DISCOVER_PHY 36# define CONFIG_SYS_RX_ETH_BUFFER 8 37# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 38# define CONFIG_HAS_ETH1 39 40# define CONFIG_SYS_FEC0_PINMUX 0 41# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 42# define MCFFEC_TOUT_LOOP 50000 43/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 44# ifndef CONFIG_SYS_DISCOVER_PHY 45# define FECDUPLEX FULL 46# define FECSPEED _100BASET 47# else 48# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50# endif 51# endif /* CONFIG_SYS_DISCOVER_PHY */ 52#endif 53 54/* Timer */ 55#define CONFIG_MCFTMR 56#undef CONFIG_MCFPIT 57 58/* I2C */ 59#define CONFIG_SYS_I2C 60#define CONFIG_SYS_I2C_FSL 61#define CONFIG_SYS_FSL_I2C_SPEED 80000 62#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 63#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 64#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 65 66#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 67#define CONFIG_UDP_CHECKSUM 68 69#ifdef CONFIG_MCFFEC 70# define CONFIG_IPADDR 192.162.1.2 71# define CONFIG_NETMASK 255.255.255.0 72# define CONFIG_SERVERIP 192.162.1.1 73# define CONFIG_GATEWAYIP 192.162.1.1 74#endif /* CONFIG_MCFFEC */ 75 76#define CONFIG_HOSTNAME M5208EVBe 77#define CONFIG_EXTRA_ENV_SETTINGS \ 78 "netdev=eth0\0" \ 79 "loadaddr=40010000\0" \ 80 "u-boot=u-boot.bin\0" \ 81 "load=tftp ${loadaddr) ${u-boot}\0" \ 82 "upd=run load; run prog\0" \ 83 "prog=prot off 0 3ffff;" \ 84 "era 0 3ffff;" \ 85 "cp.b ${loadaddr} 0 ${filesize};" \ 86 "save\0" \ 87 "" 88 89#define CONFIG_PRAM 512 /* 512 KB */ 90#define CONFIG_SYS_LONGHELP /* undef to save memory */ 91 92#ifdef CONFIG_CMD_KGDB 93# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 94#else 95# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 96#endif 97 98#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 99#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 100#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 101#define CONFIG_SYS_LOAD_ADDR 0x40010000 102 103#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 104#define CONFIG_SYS_PLL_ODR 0x36 105#define CONFIG_SYS_PLL_FDR 0x7D 106 107#define CONFIG_SYS_MBAR 0xFC000000 108 109/* 110 * Low Level Configuration Settings 111 * (address mappings, register initial values, etc.) 112 * You should know what you are doing if you make changes here. 113 */ 114/* Definitions for initial stack pointer and data area (in DPRAM) */ 115#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 116#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 117#define CONFIG_SYS_INIT_RAM_CTRL 0x221 118#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 119#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 120 121/* 122 * Start addresses for the final memory configuration 123 * (Set up by the startup code) 124 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 125 */ 126#define CONFIG_SYS_SDRAM_BASE 0x40000000 127#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 128#define CONFIG_SYS_SDRAM_CFG1 0x43711630 129#define CONFIG_SYS_SDRAM_CFG2 0x56670000 130#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 131#define CONFIG_SYS_SDRAM_EMOD 0x80010000 132#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 133 134#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 135#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 136 137#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 138#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 139 140#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 141#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 142 143/* 144 * For booting Linux, the board info and command line data 145 * have to be in the first 8 MB of memory, since this is 146 * the maximum mapped by the Linux kernel during initialization ?? 147 */ 148#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 149#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 150 151/* FLASH organization */ 152#define CONFIG_SYS_FLASH_CFI 153#ifdef CONFIG_SYS_FLASH_CFI 154# define CONFIG_FLASH_CFI_DRIVER 1 155# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 156# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 157# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 158# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 159# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 160#endif 161 162#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 163 164/* 165 * Configuration for environment 166 * Environment is embedded in u-boot in the second sector of the flash 167 */ 168#define CONFIG_ENV_OFFSET 0x2000 169#define CONFIG_ENV_SIZE 0x1000 170#define CONFIG_ENV_SECT_SIZE 0x2000 171#define CONFIG_ENV_IS_IN_FLASH 1 172 173#define LDS_BOARD_TEXT \ 174 . = DEFINED(env_offset) ? env_offset : .; \ 175 common/env_embedded.o (.text*); 176 177/* Cache Configuration */ 178#define CONFIG_SYS_CACHELINE_SIZE 16 179 180#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 181 CONFIG_SYS_INIT_RAM_SIZE - 8) 182#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 4) 184#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 185#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 186 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 187 CF_ACR_EN | CF_ACR_SM_ALL) 188#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 189 CF_CACR_DISD | CF_CACR_INVI | \ 190 CF_CACR_CEIB | CF_CACR_DCM | \ 191 CF_CACR_EUSP) 192 193/* Chipselect bank definitions */ 194/* 195 * CS0 - NOR Flash 196 * CS1 - Available 197 * CS2 - Available 198 * CS3 - Available 199 * CS4 - Available 200 * CS5 - Available 201 */ 202#define CONFIG_SYS_CS0_BASE 0 203#define CONFIG_SYS_CS0_MASK 0x007F0001 204#define CONFIG_SYS_CS0_CTRL 0x00001FA0 205 206#endif /* _M5208EVBE_H */ 207