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9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_DISPLAY_BOARDINFO
14
15
16#define CONFIG_BOOKE 1
17#define CONFIG_E500 1
18#define CONFIG_MPC8569 1
19#define CONFIG_MPC8569MDS 1
20
21#define CONFIG_FSL_ELBC 1
22
23#define CONFIG_SYS_SRIO
24#define CONFIG_SRIO1
25
26#define CONFIG_PCI 1
27#define CONFIG_PCIE1 1
28#define CONFIG_FSL_PCI_INIT 1
29#define CONFIG_PCI_INDIRECT_BRIDGE 1
30#define CONFIG_FSL_PCIE_RESET 1
31#define CONFIG_SYS_PCI_64BIT 1
32#define CONFIG_QE
33#define CONFIG_ENV_OVERWRITE
34#define CONFIG_FSL_LAW 1
35
36#ifndef __ASSEMBLY__
37extern unsigned long get_clock_freq(void);
38#endif
39
40#define CONFIG_SYS_CLK_FREQ 66666666
41#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
42
43#ifdef CONFIG_ATM
44#define CONFIG_PQ_MDS_PIB
45#define CONFIG_PQ_MDS_PIB_ATM
46#endif
47
48
49
50
51#define CONFIG_L2_CACHE
52#define CONFIG_BTB
53
54#ifndef CONFIG_SYS_TEXT_BASE
55#define CONFIG_SYS_TEXT_BASE 0xfff80000
56#endif
57
58#ifndef CONFIG_SYS_MONITOR_BASE
59#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
60#endif
61
62
63
64
65#define CONFIG_ENABLE_36BIT_PHYS 1
66
67#define CONFIG_BOARD_EARLY_INIT_F 1
68#define CONFIG_BOARD_EARLY_INIT_R 1
69#define CONFIG_HWCONFIG
70
71#define CONFIG_SYS_MEMTEST_START 0x00200000
72#define CONFIG_SYS_MEMTEST_END 0x00400000
73
74
75
76
77#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
78#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
79#define CONFIG_SYS_L2_SIZE (512 << 10)
80#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
81
82#define CONFIG_SYS_CCSRBAR 0xe0000000
83#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
84
85#if defined(CONFIG_NAND_SPL)
86#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
87#endif
88
89
90#define CONFIG_SYS_FSL_DDR3
91#undef CONFIG_FSL_DDR_INTERACTIVE
92#define CONFIG_SPD_EEPROM
93#define CONFIG_DDR_SPD
94#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
95
96#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
97
98#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
99
100#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
101
102#define CONFIG_NUM_DDR_CONTROLLERS 1
103#define CONFIG_DIMM_SLOTS_PER_CTLR 1
104#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
105
106
107#define SPD_EEPROM_ADDRESS 0x51
108
109
110#define CONFIG_SYS_SDRAM_SIZE 1024
111#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
112#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
113#define CONFIG_SYS_DDR_TIMING_3 0x00020000
114#define CONFIG_SYS_DDR_TIMING_0 0x00330004
115#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
116#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
117#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
118#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
119#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
120#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
121#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
122#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
123#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
124#define CONFIG_SYS_DDR_TIMING_4 0x00220001
125#define CONFIG_SYS_DDR_TIMING_5 0x03402400
126#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
127#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
128#define CONFIG_SYS_DDR_CDR_1 0x80040000
129#define CONFIG_SYS_DDR_CDR_2 0x00000000
130#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
131#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
132#define CONFIG_SYS_DDR_CONTROL 0xc7000000
133#define CONFIG_SYS_DDR_CONTROL2 0x24400000
134
135#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
136#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
137#define CONFIG_SYS_DDR_SBE 0x00010000
138
139#undef CONFIG_CLOCKS_IN_MHZ
140
141
142
143
144
145#define CONFIG_SYS_FLASH_BASE 0xfe000000
146#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
147
148#define CONFIG_SYS_BCSR_BASE 0xf8000000
149#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
150
151
152#define CONFIG_FLASH_BR_PRELIM 0xfe000801
153#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
154
155
156#define CONFIG_SYS_BR1_PRELIM 0xf8000801
157#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
158
159
160#define CONFIG_SYS_BR4_PRELIM 0xf8008801
161#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
162
163
164#define CONFIG_SYS_BR5_PRELIM 0xf8010801
165#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
166
167#define CONFIG_SYS_MAX_FLASH_BANKS 1
168#define CONFIG_SYS_MAX_FLASH_SECT 512
169#undef CONFIG_SYS_FLASH_CHECKSUM
170#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
171#define CONFIG_SYS_FLASH_WRITE_TOUT 500
172
173#undef CONFIG_SYS_RAMBOOT
174
175#define CONFIG_FLASH_CFI_DRIVER
176#define CONFIG_SYS_FLASH_CFI
177#define CONFIG_SYS_FLASH_EMPTY_INFO
178
179
180#ifndef CONFIG_NAND_SPL
181#define CONFIG_SYS_NAND_BASE 0xFC000000
182#else
183#define CONFIG_SYS_NAND_BASE 0xFFF00000
184#endif
185
186
187#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
188#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
189#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
190#define CONFIG_SYS_NAND_U_BOOT_START \
191 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
192#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
193#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
194#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
195
196#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
197#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
198#define CONFIG_SYS_MAX_NAND_DEVICE 1
199#define CONFIG_CMD_NAND 1
200#define CONFIG_NAND_FSL_ELBC 1
201#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
202#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
203 | (2<<BR_DECC_SHIFT) \
204 | BR_PS_8 \
205 | BR_MS_FCM \
206 | BR_V)
207#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
208 | OR_FCM_CSCT \
209 | OR_FCM_CST \
210 | OR_FCM_CHT \
211 | OR_FCM_SCY_1 \
212 | OR_FCM_TRLX \
213 | OR_FCM_EHTR)
214
215#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
216#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
217#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM
218#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM
219
220#define CONFIG_SYS_LBC_LCRR 0x00000004
221#define CONFIG_SYS_LBC_LBCR 0x00040000
222#define CONFIG_SYS_LBC_LSRT 0x20000000
223#define CONFIG_SYS_LBC_MRTPR 0x00000000
224
225#define CONFIG_SYS_INIT_RAM_LOCK 1
226#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
227#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
228
229#define CONFIG_SYS_GBL_DATA_OFFSET \
230 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
231#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
232
233#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
234#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
235
236
237#define CONFIG_CONS_INDEX 1
238#define CONFIG_SYS_NS16550_SERIAL
239#define CONFIG_SYS_NS16550_REG_SIZE 1
240#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
241#ifdef CONFIG_NAND_SPL
242#define CONFIG_NS16550_MIN_FUNCTIONS
243#endif
244
245#define CONFIG_SYS_BAUDRATE_TABLE \
246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
247
248#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
249#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
250
251
252#define CONFIG_SYS_HUSH_PARSER
253#ifdef CONFIG_SYS_HUSH_PARSER
254#endif
255
256
257#define CONFIG_OF_LIBFDT 1
258#define CONFIG_OF_BOARD_SETUP 1
259#define CONFIG_OF_STDOUT_VIA_ALIAS 1
260
261
262
263
264#define CONFIG_SYS_I2C
265#define CONFIG_SYS_I2C_FSL
266#define CONFIG_SYS_FSL_I2C_SPEED 400000
267#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
268#define CONFIG_SYS_FSL_I2C2_SPEED 400000
269#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
270#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
271#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
272#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
273
274
275
276
277#define CONFIG_ID_EEPROM
278#ifdef CONFIG_ID_EEPROM
279#define CONFIG_SYS_I2C_EEPROM_NXID
280#endif
281#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
282#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
283#define CONFIG_SYS_EEPROM_BUS_NUM 1
284
285#define PLPPAR1_I2C_BIT_MASK 0x0000000F
286#define PLPPAR1_I2C2_VAL 0x00000000
287#define PLPPAR1_ESDHC_VAL 0x0000000A
288#define PLPDIR1_I2C_BIT_MASK 0x0000000F
289#define PLPDIR1_I2C2_VAL 0x0000000F
290#define PLPDIR1_ESDHC_VAL 0x00000006
291#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
292#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
293#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
294#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
295
296
297
298
299
300#define CONFIG_SYS_PCIE1_NAME "Slot"
301#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
302#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
303#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
304#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
305#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
306#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
307#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
308#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
309
310#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
311#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
312#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
313#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
314
315#ifdef CONFIG_QE
316
317
318
319#define CONFIG_SYS_UCC_RGMII_MODE
320#undef CONFIG_SYS_UCC_RMII_MODE
321
322#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
323#define CONFIG_UEC_ETH
324#define CONFIG_ETHPRIME "UEC0"
325#define CONFIG_PHY_MODE_NEED_CHANGE
326
327#define CONFIG_UEC_ETH1
328#define CONFIG_HAS_ETH0
329
330#ifdef CONFIG_UEC_ETH1
331#define CONFIG_SYS_UEC1_UCC_NUM 0
332#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
333#if defined(CONFIG_SYS_UCC_RGMII_MODE)
334#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
335#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
336#define CONFIG_SYS_UEC1_PHY_ADDR 7
337#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
338#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
339#elif defined(CONFIG_SYS_UCC_RMII_MODE)
340#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
341#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
342#define CONFIG_SYS_UEC1_PHY_ADDR 8
343#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
344#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
345#endif
346#endif
347
348#define CONFIG_UEC_ETH2
349#define CONFIG_HAS_ETH1
350
351#ifdef CONFIG_UEC_ETH2
352#define CONFIG_SYS_UEC2_UCC_NUM 1
353#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
354#if defined(CONFIG_SYS_UCC_RGMII_MODE)
355#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
356#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
357#define CONFIG_SYS_UEC2_PHY_ADDR 1
358#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
359#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
360#elif defined(CONFIG_SYS_UCC_RMII_MODE)
361#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
362#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
363#define CONFIG_SYS_UEC2_PHY_ADDR 0x9
364#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
365#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
366#endif
367#endif
368
369#define CONFIG_UEC_ETH3
370#define CONFIG_HAS_ETH2
371
372#ifdef CONFIG_UEC_ETH3
373#define CONFIG_SYS_UEC3_UCC_NUM 2
374#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
375#if defined(CONFIG_SYS_UCC_RGMII_MODE)
376#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
377#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
378#define CONFIG_SYS_UEC3_PHY_ADDR 2
379#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
380#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
381#elif defined(CONFIG_SYS_UCC_RMII_MODE)
382#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16
383#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
384#define CONFIG_SYS_UEC3_PHY_ADDR 0xA
385#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
386#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
387#endif
388#endif
389
390#define CONFIG_UEC_ETH4
391#define CONFIG_HAS_ETH3
392
393#ifdef CONFIG_UEC_ETH4
394#define CONFIG_SYS_UEC4_UCC_NUM 3
395#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
396#if defined(CONFIG_SYS_UCC_RGMII_MODE)
397#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
398#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
399#define CONFIG_SYS_UEC4_PHY_ADDR 3
400#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
401#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
402#elif defined(CONFIG_SYS_UCC_RMII_MODE)
403#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16
404#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
405#define CONFIG_SYS_UEC4_PHY_ADDR 0xB
406#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
407#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
408#endif
409#endif
410
411#undef CONFIG_UEC_ETH6
412#define CONFIG_HAS_ETH5
413
414#ifdef CONFIG_UEC_ETH6
415#define CONFIG_SYS_UEC6_UCC_NUM 5
416#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
417#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
418#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
419#define CONFIG_SYS_UEC6_PHY_ADDR 4
420#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
421#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
422#endif
423
424#undef CONFIG_UEC_ETH8
425#define CONFIG_HAS_ETH7
426
427#ifdef CONFIG_UEC_ETH8
428#define CONFIG_SYS_UEC8_UCC_NUM 7
429#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
430#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
431#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
432#define CONFIG_SYS_UEC8_PHY_ADDR 6
433#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
434#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
435#endif
436
437#endif
438
439#if defined(CONFIG_PCI)
440
441#define CONFIG_PCI_PNP
442
443#undef CONFIG_EEPRO100
444#undef CONFIG_TULIP
445
446#undef CONFIG_PCI_SCAN_SHOW
447
448#endif
449
450
451
452
453#if defined(CONFIG_SYS_RAMBOOT)
454#else
455#define CONFIG_ENV_IS_IN_FLASH 1
456#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
457#define CONFIG_ENV_SECT_SIZE 0x20000
458#define CONFIG_ENV_SIZE 0x2000
459#endif
460
461#define CONFIG_LOADS_ECHO 1
462#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
463
464
465#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
466#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
467
468
469
470
471#define CONFIG_BOOTP_BOOTFILESIZE
472#define CONFIG_BOOTP_BOOTPATH
473#define CONFIG_BOOTP_GATEWAY
474#define CONFIG_BOOTP_HOSTNAME
475
476
477
478
479
480#define CONFIG_CMD_PING
481#define CONFIG_CMD_I2C
482#define CONFIG_CMD_MII
483#define CONFIG_CMD_IRQ
484#define CONFIG_CMD_REGINFO
485
486#if defined(CONFIG_PCI)
487 #define CONFIG_CMD_PCI
488#endif
489
490
491#undef CONFIG_WATCHDOG
492
493#define CONFIG_MMC 1
494
495#ifdef CONFIG_MMC
496#define CONFIG_FSL_ESDHC
497#define CONFIG_FSL_ESDHC_PIN_MUX
498#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
499#define CONFIG_CMD_MMC
500#define CONFIG_GENERIC_MMC
501#define CONFIG_CMD_EXT2
502#define CONFIG_CMD_FAT
503#define CONFIG_DOS_PARTITION
504#endif
505
506
507
508
509#define CONFIG_SYS_LONGHELP
510#define CONFIG_CMDLINE_EDITING
511#define CONFIG_AUTO_COMPLETE
512#define CONFIG_SYS_LOAD_ADDR 0x2000000
513#if defined(CONFIG_CMD_KGDB)
514#define CONFIG_SYS_CBSIZE 2048
515#else
516#define CONFIG_SYS_CBSIZE 512
517#endif
518#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
519
520#define CONFIG_SYS_MAXARGS 32
521#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
522
523
524
525
526
527
528
529#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
530#define CONFIG_SYS_BOOTM_LEN (64 << 20)
531
532#if defined(CONFIG_CMD_KGDB)
533#define CONFIG_KGDB_BAUDRATE 230400
534#endif
535
536
537
538
539#define CONFIG_HOSTNAME mpc8569mds
540#define CONFIG_ROOTPATH "/nfsroot"
541#define CONFIG_BOOTFILE "your.uImage"
542
543#define CONFIG_SERVERIP 192.168.1.1
544#define CONFIG_GATEWAYIP 192.168.1.1
545#define CONFIG_NETMASK 255.255.255.0
546
547#define CONFIG_LOADADDR 200000
548
549#define CONFIG_BOOTDELAY 10
550#undef CONFIG_BOOTARGS
551
552#define CONFIG_BAUDRATE 115200
553
554#define CONFIG_EXTRA_ENV_SETTINGS \
555 "netdev=eth0\0" \
556 "consoledev=ttyS0\0" \
557 "ramdiskaddr=600000\0" \
558 "ramdiskfile=your.ramdisk.u-boot\0" \
559 "fdtaddr=400000\0" \
560 "fdtfile=your.fdt.dtb\0" \
561 "nfsargs=setenv bootargs root=/dev/nfs rw " \
562 "nfsroot=$serverip:$rootpath " \
563 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
564 "console=$consoledev,$baudrate $othbootargs\0" \
565 "ramargs=setenv bootargs root=/dev/ram rw " \
566 "console=$consoledev,$baudrate $othbootargs\0" \
567
568#define CONFIG_NFSBOOTCOMMAND \
569 "run nfsargs;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $fdtaddr $fdtfile;" \
572 "bootm $loadaddr - $fdtaddr"
573
574#define CONFIG_RAMBOOTCOMMAND \
575 "run ramargs;" \
576 "tftp $ramdiskaddr $ramdiskfile;" \
577 "tftp $loadaddr $bootfile;" \
578 "bootm $loadaddr $ramdiskaddr"
579
580#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
581
582#endif
583