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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_DISPLAY_BOARDINFO
16
17
18
19
20#define CONFIG_E300 1
21#define CONFIG_MPC834x 1
22#define CONFIG_MPC8349 1
23#define CONFIG_TQM834X 1
24
25#define CONFIG_SYS_TEXT_BASE 0x80000000
26
27
28#define CONFIG_SYS_IMMR 0xff400000
29
30
31#define CONFIG_83XX_CLKIN 66666000
32
33
34
35
36
37
38
39
40
41
42#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
43#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
44
45
46#undef CONFIG_BOARD_EARLY_INIT_F
47
48
49#define CONFIG_BOARD_EARLY_INIT_R
50
51
52
53
54
55#define CONFIG_SYS_DDR_BASE 0x00000000
56#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
57#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
58#define DDR_CASLAT_25
59#undef CONFIG_DDR_ECC
60#undef CONFIG_SPD_EEPROM
61
62#undef CONFIG_SYS_DRAM_TEST
63#define CONFIG_SYS_MEMTEST_START 0x00000000
64#define CONFIG_SYS_MEMTEST_END 0x00100000
65
66
67
68
69#define CONFIG_SYS_FLASH_CFI
70#define CONFIG_FLASH_CFI_DRIVER
71#undef CONFIG_SYS_FLASH_CHECKSUM
72#define CONFIG_SYS_FLASH_BASE 0x80000000
73#define CONFIG_SYS_FLASH_SIZE 8
74#define CONFIG_SYS_FLASH_EMPTY_INFO
75#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
76
77
78
79
80
81
82
83
84
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86
87
88
89
90
91#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
92
93#define CONFIG_SYS_MAX_FLASH_SECT 512
94
95
96#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
97 | BR_MS_GPCM \
98 | BR_PS_32 \
99 | BR_V)
100
101
102#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
103 | OR_GPCM_ACS_DIV4 \
104 | OR_GPCM_SCY_5 \
105 | OR_GPCM_TRLX)
106
107#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB
108
109#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
110 | CONFIG_SYS_OR_TIMING_FLASH)
111
112#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
113
114
115#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
116
117
118#define CONFIG_SYS_BR1_PRELIM 0x00000000
119#define CONFIG_SYS_OR1_PRELIM 0x00000000
120#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
121#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
122
123#define CONFIG_SYS_BR2_PRELIM 0x00000000
124#define CONFIG_SYS_OR2_PRELIM 0x00000000
125#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
126#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
127
128#define CONFIG_SYS_BR3_PRELIM 0x00000000
129#define CONFIG_SYS_OR3_PRELIM 0x00000000
130#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
131#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
132
133
134
135
136#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
137
138#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
139# define CONFIG_SYS_RAMBOOT
140#else
141# undef CONFIG_SYS_RAMBOOT
142#endif
143
144#define CONFIG_SYS_INIT_RAM_LOCK 1
145#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
146#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
147
148#define CONFIG_SYS_GBL_DATA_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
151
152
153#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
154
155#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
156
157
158
159
160#define CONFIG_CONS_INDEX 1
161#define CONFIG_SYS_NS16550_SERIAL
162#define CONFIG_SYS_NS16550_REG_SIZE 1
163#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
164
165#define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
167
168#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
169#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
170
171
172
173
174#define CONFIG_SYS_I2C
175#define CONFIG_SYS_I2C_FSL
176#define CONFIG_SYS_FSL_I2C_SPEED 400000
177#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
178#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
179
180
181#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
182#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
183#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
184#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
185
186
187#define CONFIG_RTC_DS1337
188#define CONFIG_SYS_I2C_RTC_ADDR 0x68
189
190
191#define CONFIG_DTT_LM75 1
192#define CONFIG_DTT_SENSORS {0}
193#define CONFIG_SYS_DTT_MAX_TEMP 70
194#define CONFIG_SYS_DTT_LOW_TEMP -30
195#define CONFIG_SYS_DTT_HYSTERESIS 3
196
197
198
199
200#define CONFIG_TSEC_ENET
201#define CONFIG_MII
202
203#define CONFIG_SYS_TSEC1_OFFSET 0x24000
204#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
205#define CONFIG_SYS_TSEC2_OFFSET 0x25000
206#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
207
208#if defined(CONFIG_TSEC_ENET)
209
210#define CONFIG_TSEC1 1
211#define CONFIG_TSEC1_NAME "TSEC0"
212#define CONFIG_TSEC2 1
213#define CONFIG_TSEC2_NAME "TSEC1"
214#define TSEC1_PHY_ADDR 2
215#define TSEC2_PHY_ADDR 1
216#define TSEC1_PHYIDX 0
217#define TSEC2_PHYIDX 0
218#define TSEC1_FLAGS TSEC_GIGABIT
219#define TSEC2_FLAGS TSEC_GIGABIT
220
221
222#define CONFIG_ETHPRIME "TSEC0"
223
224#endif
225
226
227
228
229
230#define CONFIG_PCI
231
232#if defined(CONFIG_PCI)
233
234#define CONFIG_PCI_PNP
235#define CONFIG_PCI_SCAN_SHOW
236
237
238#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
239#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
240#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
241#define CONFIG_SYS_PCI1_MMIO_BASE \
242 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
243#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
244#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
245#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
246#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
247#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000
248
249#undef CONFIG_EEPRO100
250#define CONFIG_EEPRO100
251#undef CONFIG_TULIP
252
253#if !defined(CONFIG_PCI_PNP)
254 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
255 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
256 #define PCI_IDSEL_NUMBER 0x1c
257#endif
258
259#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
260
261#endif
262
263
264
265
266#define CONFIG_ENV_IS_IN_FLASH 1
267#define CONFIG_ENV_ADDR \
268 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
269#define CONFIG_ENV_SECT_SIZE 0x20000
270#define CONFIG_ENV_SIZE 0x8000
271#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
272#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
273
274#define CONFIG_LOADS_ECHO 1
275#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
276
277
278
279
280#define CONFIG_BOOTP_BOOTFILESIZE
281#define CONFIG_BOOTP_BOOTPATH
282#define CONFIG_BOOTP_GATEWAY
283#define CONFIG_BOOTP_HOSTNAME
284
285
286
287
288
289#define CONFIG_CMD_ASKENV
290#define CONFIG_CMD_DATE
291#define CONFIG_CMD_DHCP
292#define CONFIG_CMD_DTT
293#define CONFIG_CMD_EEPROM
294#define CONFIG_CMD_I2C
295#define CONFIG_CMD_JFFS2
296#define CONFIG_CMD_MII
297#define CONFIG_CMD_PING
298#define CONFIG_CMD_REGINFO
299#define CONFIG_CMD_SNTP
300
301#if defined(CONFIG_PCI)
302 #define CONFIG_CMD_PCI
303#endif
304
305
306
307
308#define CONFIG_SYS_LONGHELP
309#define CONFIG_SYS_LOAD_ADDR 0x2000000
310
311#define CONFIG_CMDLINE_EDITING 1
312#define CONFIG_AUTO_COMPLETE
313
314#define CONFIG_SYS_HUSH_PARSER 1
315
316#if defined(CONFIG_CMD_KGDB)
317 #define CONFIG_SYS_CBSIZE 1024
318#else
319 #define CONFIG_SYS_CBSIZE 256
320#endif
321
322
323#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
324#define CONFIG_SYS_MAXARGS 16
325
326#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
327
328#undef CONFIG_WATCHDOG
329
330
331#define CONFIG_OF_LIBFDT 1
332#define CONFIG_OF_BOARD_SETUP 1
333#define CONFIG_OF_STDOUT_VIA_ALIAS 1
334
335
336
337
338
339
340
341#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
342
343#define CONFIG_SYS_HRCW_LOW (\
344 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
345 HRCWL_DDR_TO_SCB_CLK_1X1 |\
346 HRCWL_CSB_TO_CLKIN_4X1 |\
347 HRCWL_VCO_1X2 |\
348 HRCWL_CORE_TO_CSB_2X1)
349
350#if defined(PCI_64BIT)
351#define CONFIG_SYS_HRCW_HIGH (\
352 HRCWH_PCI_HOST |\
353 HRCWH_64_BIT_PCI |\
354 HRCWH_PCI1_ARBITER_ENABLE |\
355 HRCWH_PCI2_ARBITER_DISABLE |\
356 HRCWH_CORE_ENABLE |\
357 HRCWH_FROM_0X00000100 |\
358 HRCWH_BOOTSEQ_DISABLE |\
359 HRCWH_SW_WATCHDOG_DISABLE |\
360 HRCWH_ROM_LOC_LOCAL_16BIT |\
361 HRCWH_TSEC1M_IN_GMII |\
362 HRCWH_TSEC2M_IN_GMII)
363#else
364#define CONFIG_SYS_HRCW_HIGH (\
365 HRCWH_PCI_HOST |\
366 HRCWH_32_BIT_PCI |\
367 HRCWH_PCI1_ARBITER_ENABLE |\
368 HRCWH_PCI2_ARBITER_DISABLE |\
369 HRCWH_CORE_ENABLE |\
370 HRCWH_FROM_0X00000100 |\
371 HRCWH_BOOTSEQ_DISABLE |\
372 HRCWH_SW_WATCHDOG_DISABLE |\
373 HRCWH_ROM_LOC_LOCAL_16BIT |\
374 HRCWH_TSEC1M_IN_GMII |\
375 HRCWH_TSEC2M_IN_GMII)
376#endif
377
378
379#define CONFIG_SYS_SICRH 0
380#define CONFIG_SYS_SICRL SICRL_LDP_A
381
382
383#define CONFIG_SYS_HID0_INIT 0x000000000
384#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
385 HID0_ENABLE_INSTRUCTION_CACHE)
386#define CONFIG_SYS_HID2 HID2_HBE
387
388#define CONFIG_HIGH_BATS 1
389
390
391#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
392 | BATL_PP_RW \
393 | BATL_MEMCOHERENCE)
394#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
395 | BATU_BL_256M \
396 | BATU_VS \
397 | BATU_VP)
398#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
399 | BATL_PP_RW \
400 | BATL_MEMCOHERENCE)
401#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
402 | BATU_BL_256M \
403 | BATU_VS \
404 | BATU_VP)
405
406
407#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
408 | BATL_PP_RW \
409 | BATL_MEMCOHERENCE)
410#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
411 | BATU_BL_128K \
412 | BATU_VS \
413 | BATU_VP)
414
415
416#ifdef CONFIG_PCI
417#define CONFIG_PCI_INDIRECT_BRIDGE
418#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
419 | BATL_PP_RW \
420 | BATL_MEMCOHERENCE)
421#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
422 | BATU_BL_256M \
423 | BATU_VS \
424 | BATU_VP)
425#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
426 | BATL_PP_RW \
427 | BATL_MEMCOHERENCE \
428 | BATL_GUARDEDSTORAGE)
429#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
430 | BATU_BL_256M \
431 | BATU_VS \
432 | BATU_VP)
433#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
434 | BATL_PP_RW \
435 | BATL_CACHEINHIBIT \
436 | BATL_GUARDEDSTORAGE)
437#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
438 | BATU_BL_16M \
439 | BATU_VS \
440 | BATU_VP)
441#else
442#define CONFIG_SYS_IBAT3L (0)
443#define CONFIG_SYS_IBAT3U (0)
444#define CONFIG_SYS_IBAT4L (0)
445#define CONFIG_SYS_IBAT4U (0)
446#define CONFIG_SYS_IBAT5L (0)
447#define CONFIG_SYS_IBAT5U (0)
448#endif
449
450
451#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
452 | BATL_PP_RW \
453 | BATL_CACHEINHIBIT \
454 | BATL_GUARDEDSTORAGE)
455#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
456 | BATU_BL_1M \
457 | BATU_VS \
458 | BATU_VP)
459
460
461#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
462 | BATL_PP_RW \
463 | BATL_CACHEINHIBIT \
464 | BATL_GUARDEDSTORAGE)
465#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
466 | BATU_BL_256M \
467 | BATU_VS \
468 | BATU_VP)
469
470#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
471#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
472#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
473#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
474#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
475#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
476#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
477#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
478#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
479#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
480#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
481#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
482#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
483#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
484#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
485#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
486
487#if defined(CONFIG_CMD_KGDB)
488#define CONFIG_KGDB_BAUDRATE 230400
489#endif
490
491
492
493
494
495
496#define CONFIG_LOADADDR 400000
497
498#define CONFIG_BOOTDELAY 6
499#undef CONFIG_BOOTARGS
500
501#define CONFIG_BAUDRATE 115200
502
503#define CONFIG_PREBOOT "echo;" \
504 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
505 "echo"
506
507#undef CONFIG_BOOTARGS
508
509#define CONFIG_EXTRA_ENV_SETTINGS \
510 "netdev=eth0\0" \
511 "hostname=tqm834x\0" \
512 "nfsargs=setenv bootargs root=/dev/nfs rw " \
513 "nfsroot=${serverip}:${rootpath}\0" \
514 "ramargs=setenv bootargs root=/dev/ram rw\0" \
515 "addip=setenv bootargs ${bootargs} " \
516 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
517 ":${hostname}:${netdev}:off panic=1\0" \
518 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
519 "flash_nfs_old=run nfsargs addip addcons;" \
520 "bootm ${kernel_addr}\0" \
521 "flash_nfs=run nfsargs addip addcons;" \
522 "bootm ${kernel_addr} - ${fdt_addr}\0" \
523 "flash_self_old=run ramargs addip addcons;" \
524 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
525 "flash_self=run ramargs addip addcons;" \
526 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
527 "net_nfs_old=tftp 400000 ${bootfile};" \
528 "run nfsargs addip addcons;bootm\0" \
529 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
530 "tftp ${fdt_addr_r} ${fdt_file}; " \
531 "run nfsargs addip addcons; " \
532 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
533 "rootpath=/opt/eldk/ppc_6xx\0" \
534 "bootfile=tqm834x/uImage\0" \
535 "fdtfile=tqm834x/tqm834x.dtb\0" \
536 "kernel_addr_r=400000\0" \
537 "fdt_addr_r=600000\0" \
538 "ramdisk_addr_r=800000\0" \
539 "kernel_addr=800C0000\0" \
540 "fdt_addr=800A0000\0" \
541 "ramdisk_addr=80300000\0" \
542 "u-boot=tqm834x/u-boot.bin\0" \
543 "load=tftp 200000 ${u-boot}\0" \
544 "update=protect off 80000000 +${filesize};" \
545 "era 80000000 +${filesize};" \
546 "cp.b 200000 80000000 ${filesize}\0" \
547 "upd=run load update\0" \
548 ""
549
550#define CONFIG_BOOTCOMMAND "run flash_self"
551
552
553
554
555
556#define CONFIG_CMD_MTDPARTS
557#define CONFIG_MTD_DEVICE
558#define CONFIG_FLASH_CFI_MTD
559#define MTDIDS_DEFAULT "nor0=TQM834x-0"
560
561
562#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
563 "1m(kernel),2m(initrd)," \
564 "-(user);" \
565
566#endif
567