LXR uboot/include/configs/iocon.h

   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12#define CONFIG_IOCON            1       /*  on a IoCon board */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16/*
  17 * Include common defines/options for all AMCC eval boards
  18 */
  19#define CONFIG_HOSTNAME         iocon
  20#define CONFIG_IDENT_STRING     " iocon 0.06"
  21#include "amcc-common.h"
  22
  23/* Reclaim some space. */
  24#undef CONFIG_SYS_LONGHELP
  25
  26#define CONFIG_BOARD_EARLY_INIT_F
  27#define CONFIG_BOARD_EARLY_INIT_R
  28#define CONFIG_LAST_STAGE_INIT
  29
  30#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  31
  32/*
  33 * Configure PLL
  34 */
  35#define PLLMR0_DEFAULT PLLMR0_266_133_66
  36#define PLLMR1_DEFAULT PLLMR1_266_133_66
  37
  38#undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
  39
  40/* new uImage format support */
  41#define CONFIG_FIT_DISABLE_SHA256
  42
  43#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  44
  45/*
  46 * Default environment variables
  47 */
  48#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  49        CONFIG_AMCC_DEF_ENV                                             \
  50        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  51        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  52        "kernel_addr=fc000000\0"                                        \
  53        "fdt_addr=fc1e0000\0"                                           \
  54        "ramdisk_addr=fc200000\0"                                       \
  55        ""
  56
  57#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  58#define CONFIG_HAS_ETH0
  59#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  60
  61/*
  62 * Commands additional to the ones defined in amcc-common.h
  63 */
  64#define CONFIG_CMD_CACHE
  65#define CONFIG_CMD_FPGAD
  66#undef CONFIG_CMD_EEPROM
  67#undef CONFIG_CMD_I2C
  68#undef CONFIG_CMD_IRQ
  69
  70/*
  71 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  72 */
  73#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  74
  75/* SDRAM timings used in datasheet */
  76#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  77#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  78#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  79#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  80#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  81
  82/*
  83 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  84 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  85 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  86 * The Linux BASE_BAUD define should match this configuration.
  87 *    baseBaud = cpuClock/(uartDivisor*16)
  88 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  89 * set Linux BASE_BAUD to 403200.
  90 */
  91#define CONFIG_CONS_INDEX               1       /* Use UART0 */
  92#undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* external serial clock */
  93#undef  CONFIG_SYS_405_UART_ERRATA_59           /* 405GP/CR Rev. D silicon */
  94#define CONFIG_SYS_BASE_BAUD            691200
  95
  96/*
  97 * I2C stuff
  98 */
  99#define CONFIG_SYS_I2C
 100#define CONFIG_SYS_I2C_PPC4XX
 101#define CONFIG_SYS_I2C_PPC4XX_CH0
 102#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 103#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 104#define CONFIG_SYS_I2C_IHS
 105
 106#define CONFIG_SYS_I2C_SPEED            400000
 107#define CONFIG_SYS_SPD_BUS_NUM          4
 108
 109#define CONFIG_PCA953X                  /* NXP PCA9554 */
 110#define CONFIG_PCA9698                  /* NXP PCA9698 */
 111
 112#define CONFIG_SYS_I2C_IHS_CH0
 113#define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 114#define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 115#define CONFIG_SYS_I2C_IHS_CH1
 116#define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 117#define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 118#define CONFIG_SYS_I2C_IHS_CH2
 119#define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 120#define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 121#define CONFIG_SYS_I2C_IHS_CH3
 122#define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 123#define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 124
 125/*
 126 * Software (bit-bang) I2C driver configuration
 127 */
 128#define CONFIG_SYS_I2C_SOFT
 129#define CONFIG_SYS_I2C_SOFT_SPEED               50000
 130#define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 131#define I2C_SOFT_DECLARATIONS2
 132#define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 133#define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 134#define I2C_SOFT_DECLARATIONS3
 135#define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 136#define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 137#define I2C_SOFT_DECLARATIONS4
 138#define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 139#define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 140
 141#define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
 142#define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
 143#define CONFIG_SYS_DP501_I2C                    {0, 1, 2, 3}
 144
 145#ifndef __ASSEMBLY__
 146void fpga_gpio_set(unsigned int bus, int pin);
 147void fpga_gpio_clear(unsigned int bus, int pin);
 148int fpga_gpio_get(unsigned int bus, int pin);
 149#endif
 150
 151#define I2C_ACTIVE      { }
 152#define I2C_TRISTATE    { }
 153#define I2C_READ \
 154        (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
 155#define I2C_SDA(bit) \
 156        do { \
 157                if (bit) \
 158                        fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
 159                else \
 160                        fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
 161        } while (0)
 162#define I2C_SCL(bit) \
 163        do { \
 164                if (bit) \
 165                        fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
 166                else \
 167                        fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
 168        } while (0)
 169#define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 170
 171/*
 172 * FLASH organization
 173 */
 174#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 175#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 176
 177#define CONFIG_SYS_FLASH_BASE           0xFC000000
 178#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 179
 180#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 181#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 182
 183#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 184#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 185
 186#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 187
 188#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 189#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 190
 191#ifdef CONFIG_ENV_IS_IN_FLASH
 192#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 193#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 194#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 195
 196/* Address and size of Redundant Environment Sector     */
 197#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 198#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 199#endif
 200
 201/*
 202 * PPC405 GPIO Configuration
 203 */
 204#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 205{ \
 206/* GPIO Core 0 */ \
 207{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 208{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 209{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 210{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 211{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 212{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 213{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 214{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5 */ \
 215{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 216{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 220{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 221{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 222{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 223{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 224{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 225{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 226{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 227{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 228{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 229{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 230{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 231{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 232{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 233{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 234{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 235{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 236{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 237{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 238{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 239} \
 240}
 241
 242/*
 243 * Definitions for initial stack pointer and data area (in data cache)
 244 */
 245/* use on chip memory (OCM) for temperary stack until sdram is tested */
 246#define CONFIG_SYS_TEMP_STACK_OCM        1
 247
 248/* On Chip Memory location */
 249#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 250#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 251#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 252#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 253
 254#define CONFIG_SYS_GBL_DATA_OFFSET \
 255        (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 256#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 257
 258/*
 259 * External Bus Controller (EBC) Setup
 260 */
 261
 262/* Memory Bank 0 (NOR-FLASH) initialization */
 263#define CONFIG_SYS_EBC_PB0AP            0xa382a880
 264#define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 265
 266/* Memory Bank 1 (NVRAM) initializatio */
 267#define CONFIG_SYS_EBC_PB1AP            0x92015480
 268#define CONFIG_SYS_EBC_PB1CR            0xFB858000
 269
 270/* Memory Bank 2 (FPGA0) initialization */
 271#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 272#define CONFIG_SYS_EBC_PB2AP            0x02825080
 273#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA0_BASE | 0x1a000)
 274
 275#define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 276#define CONFIG_SYS_FPGA_DONE(k)         0x0010
 277
 278#define CONFIG_SYS_FPGA_COUNT           1
 279
 280#define CONFIG_SYS_MCLINK_MAX           3
 281
 282#define CONFIG_SYS_FPGA_PTR \
 283        { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 284
 285/* Memory Bank 3 (Latches) initialization */
 286#define CONFIG_SYS_LATCH_BASE           0x7f200000
 287#define CONFIG_SYS_EBC_PB3AP            0x02025080
 288#define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 289
 290#define CONFIG_SYS_LATCH0_RESET         0xffef
 291#define CONFIG_SYS_LATCH0_BOOT          0xffff
 292#define CONFIG_SYS_LATCH1_RESET         0xffff
 293#define CONFIG_SYS_LATCH1_BOOT          0xffff
 294
 295/*
 296 * OSD Setup
 297 */
 298#define CONFIG_SYS_MPC92469AC
 299#define CONFIG_SYS_OSD_SCREENS          1
 300#define CONFIG_SYS_DP501_DIFFERENTIAL
 301#define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 302
 303#define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 304#define CONFIG_BITBANGMII_MULTI
 305
 306#endif  /* __CONFIG_H */
 307