1/* 2 * U-Boot - Configuration file for IP04 board (having BF532 processor) 3 * 4 * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com 5 * 6 * Copyright (c) 2005-2010 Analog Devices Inc. 7 * 8 * (C) Copyright 2000-2004 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 11 * Licensed under the GPL-2 or later. 12 */ 13 14#ifndef __CONFIG_IP04_H__ 15#define __CONFIG_IP04_H__ 16 17#include <asm/config-pre.h> 18 19 20/* 21 * Processor Settings 22 */ 23#define CONFIG_BFIN_CPU bf532-0.5 24#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND 25 26 27/* 28 * Clock Settings 29 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 30 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 31 */ 32/* CONFIG_CLKIN_HZ is any value in Hz */ 33#define CONFIG_CLKIN_HZ 10000000 34/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 35/* 1 = CLKIN / 2 */ 36#define CONFIG_CLKIN_HALF 0 37/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 38/* 1 = bypass PLL */ 39#define CONFIG_PLL_BYPASS 0 40/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 41/* Values can range from 0-63 (where 0 means 64) */ 42#define CONFIG_VCO_MULT 40 43/* CCLK_DIV controls the core clock divider */ 44/* Values can be 1, 2, 4, or 8 ONLY */ 45#define CONFIG_CCLK_DIV 1 46/* SCLK_DIV controls the system clock divider */ 47/* Values can range from 1-15 */ 48#define CONFIG_SCLK_DIV 3 49 50 51/* 52 * Memory Settings 53 */ 54#define CONFIG_MEM_ADD_WDTH 10 55#define CONFIG_MEM_SIZE 64 56 57#define CONFIG_EBIU_SDRRC_VAL 0x408 58#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd 59 60#define CONFIG_EBIU_AMGCTL_VAL 0xFF 61#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 62#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 63 64#define CONFIG_SYS_MONITOR_LEN (384 * 1024) 65#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 66 67 68/* 69 * Network Settings 70 */ 71#define ADI_CMDS_NETWORK 1 72#define CONFIG_HOSTNAME IP04 73 74#define CONFIG_DRIVER_DM9000 1 75#define CONFIG_DM9000_NO_SROM 76#define CONFIG_DM9000_BASE 0x20100000 77#define DM9000_IO CONFIG_DM9000_BASE 78#define DM9000_DATA (CONFIG_DM9000_BASE + 2) 79 80 81/* 82 * Flash Settings 83 */ 84#define CONFIG_ENV_OVERWRITE 1 85#define CONFIG_SYS_NO_FLASH /* we have only NAND */ 86 87 88/* 89 * SPI Settings 90 */ 91#define CONFIG_BFIN_SPI 92#define CONFIG_ENV_SPI_MAX_HZ 30000000 93#define CONFIG_SF_DEFAULT_SPEED 30000000 94 95 96/* 97 * Env Storage Settings 98 */ 99#define CONFIG_ENV_IS_IN_SPI_FLASH 100#define CONFIG_PREBOOT "echo starting from spi flash" 101#define CONFIG_ENV_OFFSET 0x30000 102#define CONFIG_ENV_SIZE 0x10000 103#define CONFIG_ENV_SECT_SIZE 0x10000 104 105 106/* 107 * NAND Settings 108 */ 109#define CONFIG_NAND_PLAT 110#define CONFIG_SYS_NAND_BASE 0x20000000 111#define CONFIG_SYS_MAX_NAND_DEVICE 1 112 113#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) 114#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) 115#define BFIN_NAND_WRITE(addr, cmd) \ 116 do { \ 117 bfin_write8(addr, cmd); \ 118 SSYNC(); \ 119 } while (0) 120 121#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) 122#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) 123#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 124 125 126/* 127 * Misc Settings 128 */ 129#define CONFIG_BAUDRATE 115200 130#define CONFIG_UART_CONSOLE 0 131 132#undef CONFIG_SHOW_BOOT_PROGRESS 133/* Enable this if bootretry required; currently it's disabled */ 134#define CONFIG_BOOT_RETRY_TIME -1 135#define CONFIG_BOOTCOMMAND "run nandboot" 136 137 138/* 139 * Pull in common ADI header for remaining command/environment setup 140 */ 141#include <configs/bfin_adi_common.h> 142 143#endif 144