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19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23
24
25#define CONFIG_MPC8641 1
26#define CONFIG_SBC8641D 1
27#define CONFIG_MP 1
28#define CONFIG_LINUX_RESET_VEC 0x100
29
30#define CONFIG_SYS_TEXT_BASE 0xfff00000
31
32#ifdef RUN_DIAG
33#define CONFIG_SYS_DIAG_ADDR 0xff800000
34#endif
35
36#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
37
38
39
40
41
42#define CONFIG_SYS_SCRATCH_VA 0xe8000000
43
44#define CONFIG_SYS_SRIO
45#define CONFIG_SRIO1
46
47#define CONFIG_PCI 1
48#define CONFIG_PCIE1 1
49#define CONFIG_PCIE2 1
50#define CONFIG_FSL_PCI_INIT 1
51#define CONFIG_PCI_INDIRECT_BRIDGE 1
52#define CONFIG_FSL_LAW 1
53
54#define CONFIG_TSEC_ENET
55#define CONFIG_ENV_OVERWRITE
56
57#define CONFIG_BAT_RW 1
58#define CONFIG_HIGH_BATS 1
59
60#undef CONFIG_SPD_EEPROM
61#undef CONFIG_DDR_ECC
62#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
63#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
64#define CONFIG_NUM_DDR_CONTROLLERS 2
65#define CACHE_LINE_INTERLEAVING 0x20000000
66#define PAGE_INTERLEAVING 0x21000000
67#define BANK_INTERLEAVING 0x22000000
68#define SUPER_BANK_INTERLEAVING 0x23000000
69
70
71#define CONFIG_ALTIVEC 1
72
73
74
75
76#define CONFIG_SYS_L2
77#define L2_INIT 0
78#define L2_ENABLE (L2CR_L2E)
79
80#ifndef CONFIG_SYS_CLK_FREQ
81#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
82#endif
83
84#define CONFIG_BOARD_EARLY_INIT_F 1
85
86#undef CONFIG_SYS_DRAM_TEST
87#define CONFIG_SYS_MEMTEST_START 0x00200000
88#define CONFIG_SYS_MEMTEST_END 0x00400000
89
90
91
92
93
94#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
95#define CONFIG_SYS_CCSRBAR 0xf8000000
96#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
97
98#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
99#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
100#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
101
102
103
104
105#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000
107#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
109#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
110#define CONFIG_VERY_BIG_RAM
111
112#define CONFIG_NUM_DDR_CONTROLLERS 2
113#define CONFIG_DIMM_SLOTS_PER_CTLR 2
114#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
115
116#if defined(CONFIG_SPD_EEPROM)
117
118
119
120 #define SPD_EEPROM_ADDRESS1 0x51
121 #define SPD_EEPROM_ADDRESS2 0x52
122 #define SPD_EEPROM_ADDRESS3 0x53
123 #define SPD_EEPROM_ADDRESS4 0x54
124
125#else
126
127
128
129
130 #define CONFIG_SYS_SDRAM_SIZE 512
131
132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
133 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
134 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
135 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
136 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
137 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
138 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
139 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
141 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
142 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
143 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
144 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
145 #define CONFIG_SYS_DDR_CFG_2 0x24401000
146 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
147 #define CONFIG_SYS_DDR_MODE_2 0x00000000
148 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
149 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
150 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
151 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
152 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
153
154 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
155 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
156 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
157 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
158 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
159 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
160 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
161 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
162 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
163 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
164 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
165 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
166 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
167 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
168 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
169 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
170 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
171 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
172 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
173 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
174 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
175
176
177#endif
178
179
180
181
182
183
184
185#define CONFIG_SYS_FLASH_BASE 0xff000000
186
187
188#define CONFIG_SYS_BR0_PRELIM 0xff001001
189#define CONFIG_SYS_OR0_PRELIM 0xff006e65
190
191
192#define CONFIG_SYS_BR1_PRELIM 0xf0000801
193#define CONFIG_SYS_OR1_PRELIM 0xffff6e65
194
195
196#define CONFIG_SYS_BR2_PRELIM 0xf1000801
197#define CONFIG_SYS_OR2_PRELIM 0xfff06e65
198
199
200#define CONFIG_SYS_BR3_PRELIM 0xe0001861
201#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
202#define CONFIG_SYS_BR4_PRELIM 0xe4001861
203#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
204
205
206#define CONFIG_SYS_BR5_PRELIM 0xe8001001
207#define CONFIG_SYS_OR5_PRELIM 0xf8006e65
208
209
210#define CONFIG_SYS_BR6_PRELIM 0xf4000801
211#define CONFIG_SYS_OR6_PRELIM 0xfff06e65
212
213
214#define CONFIG_SYS_BR7_PRELIM 0xf2000801
215#define CONFIG_SYS_OR7_PRELIM 0xfff06e65
216
217#define CONFIG_SYS_MAX_FLASH_BANKS 1
218#define CONFIG_SYS_MAX_FLASH_SECT 131
219
220#undef CONFIG_SYS_FLASH_CHECKSUM
221#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
222#define CONFIG_SYS_FLASH_WRITE_TOUT 500
223#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
224#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
225
226#define CONFIG_FLASH_CFI_DRIVER
227#define CONFIG_SYS_FLASH_CFI
228#define CONFIG_SYS_WRITE_SWAPPED_DATA
229#define CONFIG_SYS_FLASH_EMPTY_INFO
230#define CONFIG_SYS_FLASH_PROTECTION
231
232#undef CONFIG_CLOCKS_IN_MHZ
233
234#define CONFIG_SYS_INIT_RAM_LOCK 1
235#ifndef CONFIG_SYS_INIT_RAM_LOCK
236#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
237#else
238#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
239#endif
240#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
241
242#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
243#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
244
245#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
246#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
247
248
249#define CONFIG_CONS_INDEX 1
250#define CONFIG_SYS_NS16550_SERIAL
251#define CONFIG_SYS_NS16550_REG_SIZE 1
252#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
253
254#define CONFIG_SYS_BAUDRATE_TABLE \
255 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
256
257#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
258#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
259
260
261#define CONFIG_SYS_HUSH_PARSER
262#ifdef CONFIG_SYS_HUSH_PARSER
263#endif
264
265
266
267
268#define CONFIG_OF_LIBFDT 1
269#define CONFIG_OF_BOARD_SETUP 1
270#define CONFIG_OF_STDOUT_VIA_ALIAS 1
271
272
273
274
275#define CONFIG_SYS_I2C
276#define CONFIG_SYS_I2C_FSL
277#define CONFIG_SYS_FSL_I2C_SPEED 400000
278#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
279#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
280#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
281
282
283
284
285#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000
286#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
287#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
288
289
290
291
292
293#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
294#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
295#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
296#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
297#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
298#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
299#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
300#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000
301
302#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
303#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
304#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
305#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
306#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
307#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
308#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
309#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000
310
311#if defined(CONFIG_PCI)
312
313#define CONFIG_PCI_SCAN_SHOW
314
315#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
316
317#define CONFIG_PCI_PNP
318
319#undef CONFIG_EEPRO100
320#undef CONFIG_TULIP
321
322#if !defined(CONFIG_PCI_PNP)
323 #define PCI_ENET0_IOADDR 0xe0000000
324 #define PCI_ENET0_MEMADDR 0xe0000000
325 #define PCI_IDSEL_NUMBER 0x0c
326#endif
327
328#define CONFIG_PCI_SCAN_SHOW
329
330#define CONFIG_DOS_PARTITION
331#undef CONFIG_SCSI_AHCI
332
333#ifdef CONFIG_SCSI_AHCI
334#define CONFIG_SATA_ULI5288
335#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
336#define CONFIG_SYS_SCSI_MAX_LUN 1
337#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
338#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
339#endif
340
341#endif
342
343#if defined(CONFIG_TSEC_ENET)
344
345
346
347#define CONFIG_TSEC1 1
348#define CONFIG_TSEC1_NAME "eTSEC1"
349#define CONFIG_TSEC2 1
350#define CONFIG_TSEC2_NAME "eTSEC2"
351#define CONFIG_TSEC3 1
352#define CONFIG_TSEC3_NAME "eTSEC3"
353#define CONFIG_TSEC4 1
354#define CONFIG_TSEC4_NAME "eTSEC4"
355
356#define TSEC1_PHY_ADDR 0x1F
357#define TSEC2_PHY_ADDR 0x00
358#define TSEC3_PHY_ADDR 0x01
359#define TSEC4_PHY_ADDR 0x02
360#define TSEC1_PHYIDX 0
361#define TSEC2_PHYIDX 0
362#define TSEC3_PHYIDX 0
363#define TSEC4_PHYIDX 0
364#define TSEC1_FLAGS TSEC_GIGABIT
365#define TSEC2_FLAGS TSEC_GIGABIT
366#define TSEC3_FLAGS TSEC_GIGABIT
367#define TSEC4_FLAGS TSEC_GIGABIT
368
369#define CONFIG_SYS_TBIPA_VALUE 0x1e
370
371#define CONFIG_ETHPRIME "eTSEC1"
372
373#endif
374
375
376
377
378
379#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
380#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
381#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
382#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
383
384
385
386
387
388
389
390#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
391 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
392#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
393#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
394#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
395
396
397
398
399
400#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
401 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
402#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
403#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
404#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
405
406
407
408
409
410#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
411 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
412#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
413#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
414#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
415
416#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
417#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
418 | BATL_PP_RW | BATL_CACHEINHIBIT \
419 | BATL_GUARDEDSTORAGE)
420#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
421 | BATU_BL_1M | BATU_VS | BATU_VP)
422#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
423 | BATL_PP_RW | BATL_CACHEINHIBIT)
424#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
425#endif
426
427
428
429
430
431
432
433#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
434 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
435#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
436#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
437#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
438
439
440
441
442
443#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
444#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
445#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
446#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
447
448
449
450
451
452#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
453 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
454#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
455#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
456#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
457
458
459#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
460 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
461#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
462#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
463 | BATL_MEMCOHERENCE)
464#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
465
466#define CONFIG_SYS_DBAT7L 0x00000000
467#define CONFIG_SYS_DBAT7U 0x00000000
468#define CONFIG_SYS_IBAT7L 0x00000000
469#define CONFIG_SYS_IBAT7U 0x00000000
470
471
472
473
474#define CONFIG_ENV_IS_IN_FLASH 1
475#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
476#define CONFIG_ENV_SECT_SIZE 0x20000
477#define CONFIG_ENV_SIZE 0x2000
478
479#define CONFIG_LOADS_ECHO 1
480#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
481
482#define CONFIG_CMD_PING
483#define CONFIG_CMD_I2C
484#define CONFIG_CMD_REGINFO
485
486#if defined(CONFIG_PCI)
487 #define CONFIG_CMD_PCI
488#endif
489
490#undef CONFIG_WATCHDOG
491
492
493
494
495#define CONFIG_SYS_LONGHELP
496#define CONFIG_SYS_LOAD_ADDR 0x2000000
497#define CONFIG_CMDLINE_EDITING 1
498
499#if defined(CONFIG_CMD_KGDB)
500 #define CONFIG_SYS_CBSIZE 1024
501#else
502 #define CONFIG_SYS_CBSIZE 256
503#endif
504
505#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
506#define CONFIG_SYS_MAXARGS 16
507#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
508
509
510
511
512
513
514#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
515
516
517#define CONFIG_SYS_DCACHE_SIZE 32768
518#define CONFIG_SYS_CACHELINE_SIZE 32
519#if defined(CONFIG_CMD_KGDB)
520#define CONFIG_SYS_CACHELINE_SHIFT 5
521#endif
522
523#if defined(CONFIG_CMD_KGDB)
524#define CONFIG_KGDB_BAUDRATE 230400
525#endif
526
527
528
529
530
531#define CONFIG_HAS_ETH0 1
532#define CONFIG_HAS_ETH1 1
533#define CONFIG_HAS_ETH2 1
534#define CONFIG_HAS_ETH3 1
535
536#define CONFIG_IPADDR 192.168.0.50
537
538#define CONFIG_HOSTNAME sbc8641d
539#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
540#define CONFIG_BOOTFILE "uImage"
541
542#define CONFIG_SERVERIP 192.168.0.2
543#define CONFIG_GATEWAYIP 192.168.0.1
544#define CONFIG_NETMASK 255.255.255.0
545
546
547#define CONFIG_LOADADDR 1000000
548
549#define CONFIG_BOOTDELAY 10
550#undef CONFIG_BOOTARGS
551
552#define CONFIG_BAUDRATE 115200
553
554#define CONFIG_EXTRA_ENV_SETTINGS \
555 "netdev=eth0\0" \
556 "consoledev=ttyS0\0" \
557 "ramdiskaddr=2000000\0" \
558 "ramdiskfile=uRamdisk\0" \
559 "dtbaddr=400000\0" \
560 "dtbfile=sbc8641d.dtb\0" \
561 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
562 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
563 "maxcpus=1"
564
565#define CONFIG_NFSBOOTCOMMAND \
566 "setenv bootargs root=/dev/nfs rw " \
567 "nfsroot=$serverip:$rootpath " \
568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
569 "console=$consoledev,$baudrate $othbootargs;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $dtbaddr $dtbfile;" \
572 "bootm $loadaddr - $dtbaddr"
573
574#define CONFIG_RAMBOOTCOMMAND \
575 "setenv bootargs root=/dev/ram rw " \
576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
577 "console=$consoledev,$baudrate $othbootargs;" \
578 "tftp $ramdiskaddr $ramdiskfile;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $dtbaddr $dtbfile;" \
581 "bootm $loadaddr $ramdiskaddr $dtbaddr"
582
583#define CONFIG_FLASHBOOTCOMMAND \
584 "setenv bootargs root=/dev/ram rw " \
585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
586 "console=$consoledev,$baudrate $othbootargs;" \
587 "bootm ffd00000 ffb00000 ffa00000"
588
589#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
590
591#endif
592