LXR uboot/arch/arm/cpu/armv7/ls102xa/fsl

   1/*
   2 * Copyright 2014 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/io.h>
   9
  10#include "fsl_epu.h"
  11
  12/**
  13 * fsl_epu_clean - Clear EPU registers
  14 */
  15void fsl_epu_clean(void *epu_base)
  16{
  17        u32 offset;
  18
  19        /* follow the exact sequence to clear the registers */
  20        /* Clear EPACRn */
  21        for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
  22                out_be32(epu_base + offset, 0);
  23
  24        /* Clear EPEVTCRn */
  25        for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
  26                out_be32(epu_base + offset, 0);
  27
  28        /* Clear EPGCR */
  29        out_be32(epu_base + EPGCR, 0);
  30
  31        /* Clear EPSMCRn */
  32        for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
  33                out_be32(epu_base + offset, 0);
  34
  35        /* Clear EPCCRn */
  36        for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
  37                out_be32(epu_base + offset, 0);
  38
  39        /* Clear EPCMPRn */
  40        for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
  41                out_be32(epu_base + offset, 0);
  42
  43        /* Clear EPCTRn */
  44        for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
  45                out_be32(epu_base + offset, 0);
  46
  47        /* Clear EPIMCRn */
  48        for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
  49                out_be32(epu_base + offset, 0);
  50
  51        /* Clear EPXTRIGCRn */
  52        out_be32(epu_base + EPXTRIGCR, 0);
  53
  54        /* Clear EPECRn */
  55        for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
  56                out_be32(epu_base + offset, 0);
  57}
  58