1/* 2 * Keystone2: Common SoC definitions, structures etc. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9#ifndef __ASM_ARCH_HARDWARE_H 10#define __ASM_ARCH_HARDWARE_H 11 12#include <config.h> 13 14#ifndef __ASSEMBLY__ 15 16#include <linux/sizes.h> 17#include <asm/io.h> 18 19#define REG(addr) (*(volatile unsigned int *)(addr)) 20#define REG_P(addr) ((volatile unsigned int *)(addr)) 21 22typedef volatile unsigned int dv_reg; 23typedef volatile unsigned int *dv_reg_p; 24 25#endif 26 27#define KS2_DDRPHY_PIR_OFFSET 0x04 28#define KS2_DDRPHY_PGCR0_OFFSET 0x08 29#define KS2_DDRPHY_PGCR1_OFFSET 0x0C 30#define KS2_DDRPHY_PGSR0_OFFSET 0x10 31#define KS2_DDRPHY_PGSR1_OFFSET 0x14 32#define KS2_DDRPHY_PLLCR_OFFSET 0x18 33#define KS2_DDRPHY_PTR0_OFFSET 0x1C 34#define KS2_DDRPHY_PTR1_OFFSET 0x20 35#define KS2_DDRPHY_PTR2_OFFSET 0x24 36#define KS2_DDRPHY_PTR3_OFFSET 0x28 37#define KS2_DDRPHY_PTR4_OFFSET 0x2C 38#define KS2_DDRPHY_DCR_OFFSET 0x44 39 40#define KS2_DDRPHY_DTPR0_OFFSET 0x48 41#define KS2_DDRPHY_DTPR1_OFFSET 0x4C 42#define KS2_DDRPHY_DTPR2_OFFSET 0x50 43 44#define KS2_DDRPHY_MR0_OFFSET 0x54 45#define KS2_DDRPHY_MR1_OFFSET 0x58 46#define KS2_DDRPHY_MR2_OFFSET 0x5C 47#define KS2_DDRPHY_DTCR_OFFSET 0x68 48#define KS2_DDRPHY_PGCR2_OFFSET 0x8C 49 50#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 51#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 52#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 53#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 54 55#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0 56#define KS2_DDRPHY_DATX8_5_OFFSET 0x300 57#define KS2_DDRPHY_DATX8_6_OFFSET 0x340 58#define KS2_DDRPHY_DATX8_7_OFFSET 0x380 59#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 60 61#define IODDRM_MASK 0x00000180 62#define ZCKSEL_MASK 0x01800000 63#define CL_MASK 0x00000072 64#define WR_MASK 0x00000E00 65#define BL_MASK 0x00000003 66#define RRMODE_MASK 0x00040000 67#define UDIMM_MASK 0x20000000 68#define BYTEMASK_MASK 0x0003FC00 69#define MPRDQ_MASK 0x00000080 70#define PDQ_MASK 0x00000070 71#define NOSRA_MASK 0x08000000 72#define ECC_MASK 0x00000001 73 74/* DDR3 definitions */ 75#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 76#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 77#define KS2_DDR3A_DDRPHYC 0x02329000 78 79#define KS2_DDR3_MIDR_OFFSET 0x00 80#define KS2_DDR3_STATUS_OFFSET 0x04 81#define KS2_DDR3_SDCFG_OFFSET 0x08 82#define KS2_DDR3_SDRFC_OFFSET 0x10 83#define KS2_DDR3_SDTIM1_OFFSET 0x18 84#define KS2_DDR3_SDTIM2_OFFSET 0x1C 85#define KS2_DDR3_SDTIM3_OFFSET 0x20 86#define KS2_DDR3_SDTIM4_OFFSET 0x28 87#define KS2_DDR3_PMCTL_OFFSET 0x38 88#define KS2_DDR3_ZQCFG_OFFSET 0xC8 89 90#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 91 92/* DDR3 ECC */ 93#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC 94#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4 95#define KS2_DDR3_ECC_CTRL_OFFSET 0x110 96#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114 97#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130 98#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C 99 100/* DDR3 ECC Interrupt Status register */ 101#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5) 102#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4) 103#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3) 104 105/* DDR3 ECC Control register */ 106#define KS2_DDR3_ECC_EN BIT(31) 107#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30) 108#define KS2_DDR3_ECC_VERIFY_EN BIT(29) 109#define KS2_DDR3_ECC_RMW_EN BIT(28) 110#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0) 111 112#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \ 113 KS2_DDR3_ECC_ADDR_RNG_PROT | \ 114 KS2_DDR3_ECC_VERIFY_EN) 115 116/* EDMA */ 117#define KS2_EDMA0_BASE 0x02700000 118 119/* EDMA3 register offsets */ 120#define KS2_EDMA_QCHMAP0 0x0200 121#define KS2_EDMA_IPR 0x1068 122#define KS2_EDMA_ICR 0x1070 123#define KS2_EDMA_QEECR 0x1088 124#define KS2_EDMA_QEESR 0x108c 125#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) 126 127/* NETCP pktdma */ 128#ifdef CONFIG_SOC_K2G 129#define KS2_NETCP_PDMA_RX_FREE_QUEUE 113 130#define KS2_NETCP_PDMA_RX_RCV_QUEUE 114 131#else 132#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 133#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 134#endif 135 136/* Chip Interrupt Controller */ 137#define KS2_CIC2_BASE 0x02608000 138 139/* Chip Interrupt Controller register offsets */ 140#define KS2_CIC_CTRL 0x04 141#define KS2_CIC_HOST_CTRL 0x0C 142#define KS2_CIC_GLOBAL_ENABLE 0x10 143#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28 144#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 145#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) 146 147#define KS2_UART0_BASE 0x02530c00 148#define KS2_UART1_BASE 0x02531000 149 150/* Boot Config */ 151#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 152#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) 153#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) 154#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c) 155#define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20) 156#define KS2_ETHERNET_RGMII 2 157 158/* PSC */ 159#define KS2_PSC_BASE 0x02350000 160#define KS2_LPSC_GEM_0 15 161#define KS2_LPSC_TETRIS 52 162#define KS2_TETRIS_PWR_DOMAIN 31 163#define KS2_GEM_0_PWR_DOMAIN 8 164 165/* Chip configuration unlock codes and registers */ 166#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) 167#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) 168#define KS2_KICK0_MAGIC 0x83e70b13 169#define KS2_KICK1_MAGIC 0x95a4f1e0 170 171/* PLL control registers */ 172#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) 173#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) 174#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) 175#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) 176#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) 177#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) 178#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) 179#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) 180#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) 181#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) 182#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390) 183#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394) 184 185#define KS2_PLL_CNTRL_BASE 0x02310000 186#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE 187#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) 188#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) 189#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec) 190#define KS2_RSTCTRL_KEY 0x5a69 191#define KS2_RSTCTRL_MASK 0xffff0000 192#define KS2_RSTCTRL_SWRST 0xfffe0000 193#define KS2_RSTYPE_PLL_SOFT BIT(13) 194 195/* SPI */ 196#ifdef CONFIG_SOC_K2G 197#define KS2_SPI0_BASE 0x21805400 198#define KS2_SPI1_BASE 0x21805800 199#define KS2_SPI2_BASE 0x21805c00 200#define KS2_SPI3_BASE 0x21806000 201#else 202#define KS2_SPI0_BASE 0x21000400 203#define KS2_SPI1_BASE 0x21000600 204#define KS2_SPI2_BASE 0x21000800 205#define KS2_SPI_BASE KS2_SPI0_BASE 206#endif 207 208/* AEMIF */ 209#define KS2_AEMIF_CNTRL_BASE 0x21000a00 210#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE 211 212/* Flag from ks2_debug options to check if DSPs need to stay ON */ 213#define DBG_LEAVE_DSPS_ON 0x1 214 215/* MSMC control */ 216#define KS2_MSMC_CTRL_BASE 0x0bc00000 217#define KS2_MSMC_DATA_BASE 0x0c000000 218 219/* KS2 Generic Privilege ID Settings for MSMC2 */ 220#define KS2_MSMC_SEGMENT_C6X_0 0 221#define KS2_MSMC_SEGMENT_C6X_1 1 222#define KS2_MSMC_SEGMENT_C6X_2 2 223#define KS2_MSMC_SEGMENT_C6X_3 3 224#define KS2_MSMC_SEGMENT_C6X_4 4 225#define KS2_MSMC_SEGMENT_C6X_5 5 226#define KS2_MSMC_SEGMENT_C6X_6 6 227#define KS2_MSMC_SEGMENT_C6X_7 7 228 229#define KS2_MSMC_SEGMENT_DEBUG 12 230 231/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ 232#define K2HKLE_MSMC_SEGMENT_ARM 8 233#define K2HKLE_MSMC_SEGMENT_NETCP 9 234#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10 235#define K2HKLE_MSMC_SEGMENT_PCIE0 11 236 237/* K2HK specific Privilege ID Settings */ 238#define K2HKE_MSMC_SEGMENT_HYPERLINK 14 239 240/* K2L specific Privilege ID Settings */ 241#define K2L_MSMC_SEGMENT_PCIE1 14 242 243/* K2E specific Privilege ID Settings */ 244#define K2E_MSMC_SEGMENT_PCIE1 13 245#define K2E_MSMC_SEGMENT_TSIP 15 246 247/* K2G specific Privilege ID Settings */ 248#define K2G_MSMC_SEGMENT_ARM 1 249#define K2G_MSMC_SEGMENT_ICSS0 2 250#define K2G_MSMC_SEGMENT_ICSS1 3 251#define K2G_MSMC_SEGMENT_NSS 4 252#define K2G_MSMC_SEGMENT_PCIE 5 253#define K2G_MSMC_SEGMENT_USB 6 254#define K2G_MSMC_SEGMENT_MLB 8 255#define K2G_MSMC_SEGMENT_PMMC 9 256#define K2G_MSMC_SEGMENT_DSS 10 257#define K2G_MSMC_SEGMENT_MMC 11 258 259/* MSMC segment size shift bits */ 260#define KS2_MSMC_SEG_SIZE_SHIFT 12 261#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) 262#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ 263 KS2_MSMC_SEG_SIZE_SHIFT) 264 265/* Device speed */ 266#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) 267#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) 268#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) 269 270/* Queue manager */ 271#ifdef CONFIG_SOC_K2G 272#define KS2_QM_BASE_ADDRESS 0x040C0000 273#define KS2_QM_CONF_BASE 0x04040000 274#define KS2_QM_DESC_SETUP_BASE 0x04080000 275#define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */ 276#define KS2_QM_INTD_CONF_BASE 0x0 277#define KS2_QM_PDSP1_CMD_BASE 0x0 278#define KS2_QM_PDSP1_CTRL_BASE 0x0 279#define KS2_QM_PDSP1_IRAM_BASE 0x0 280#define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000 281#define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200 282#define KS2_QM_QUEUE_STATUS_BASE 0x04100000 283#define KS2_QM_LINK_RAM_BASE 0x04020000 284#define KS2_QM_REGION_NUM 8 285#define KS2_QM_QPOOL_NUM 112 286#else 287#define KS2_QM_BASE_ADDRESS 0x23a80000 288#define KS2_QM_CONF_BASE 0x02a02000 289#define KS2_QM_DESC_SETUP_BASE 0x02a03000 290#define KS2_QM_STATUS_RAM_BASE 0x02a06000 291#define KS2_QM_INTD_CONF_BASE 0x02a0c000 292#define KS2_QM_PDSP1_CMD_BASE 0x02a20000 293#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000 294#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000 295#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000 296#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 297#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 298#define KS2_QM_LINK_RAM_BASE 0x00100000 299#define KS2_QM_REGION_NUM 64 300#define KS2_QM_QPOOL_NUM 4000 301#endif 302 303/* USB */ 304#define KS2_USB_SS_BASE 0x02680000 305#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) 306#define KS2_DEV_USB_PHY_BASE 0x02620738 307#define KS2_USB_PHY_CFG_BASE 0x02630000 308 309#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) 310 311/* SGMII SerDes */ 312#define KS2_SGMII_SERDES_BASE 0x0232a000 313 314/* JTAG ID register */ 315#define JTAGID_VARIANT_SHIFT 28 316#define JTAGID_VARIANT_MASK (0xf << 28) 317#define JTAGID_PART_NUM_SHIFT 12 318#define JTAGID_PART_NUM_MASK (0xffff << 12) 319 320/* PART NUMBER definitions */ 321#define CPU_66AK2Hx 0xb981 322#define CPU_66AK2Ex 0xb9a6 323#define CPU_66AK2Lx 0xb9a7 324#define CPU_66AK2Gx 0xbb06 325 326/* DEVSPEED register */ 327#define DEVSPEED_DEVSPEED_SHIFT 16 328#define DEVSPEED_DEVSPEED_MASK (0xfff << 16) 329#define DEVSPEED_ARMSPEED_SHIFT 0 330#define DEVSPEED_ARMSPEED_MASK 0xfff 331#define DEVSPEED_NUMSPDS 12 332 333#ifdef CONFIG_SOC_K2HK 334#include <asm/arch/hardware-k2hk.h> 335#endif 336 337#ifdef CONFIG_SOC_K2E 338#include <asm/arch/hardware-k2e.h> 339#endif 340 341#ifdef CONFIG_SOC_K2L 342#include <asm/arch/hardware-k2l.h> 343#endif 344 345#ifdef CONFIG_SOC_K2G 346#include <asm/arch/hardware-k2g.h> 347#endif 348 349#ifndef __ASSEMBLY__ 350 351static inline u16 get_part_number(void) 352{ 353 u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG); 354 355 return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT; 356} 357 358static inline u8 cpu_is_k2hk(void) 359{ 360 return get_part_number() == CPU_66AK2Hx; 361} 362 363static inline u8 cpu_is_k2e(void) 364{ 365 return get_part_number() == CPU_66AK2Ex; 366} 367 368static inline u8 cpu_is_k2l(void) 369{ 370 return get_part_number() == CPU_66AK2Lx; 371} 372 373static inline u8 cpu_is_k2g(void) 374{ 375 return get_part_number() == CPU_66AK2Gx; 376} 377 378static inline u8 cpu_revision(void) 379{ 380 u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG); 381 u8 rev = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT; 382 383 return rev; 384} 385 386int cpu_to_bus(u32 *ptr, u32 length); 387void sdelay(unsigned long); 388 389#endif 390 391#endif /* __ASM_ARCH_HARDWARE_H */ 392