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9#ifndef ARCH_SG_REGS_H
10#define ARCH_SG_REGS_H
11
12
13#define SG_CTRL_BASE 0x5f800000
14#define SG_DBG_BASE 0x5f900000
15
16
17#define SG_REVISION (SG_CTRL_BASE | 0x0000)
18#define SG_REVISION_TYPE_SHIFT 16
19#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
20#define SG_REVISION_MODEL_SHIFT 8
21#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
22#define SG_REVISION_REV_SHIFT 0
23#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
24
25
26#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
27
28#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
29#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
30#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
31#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
32#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
33#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
34#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
35#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
36#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
37
38#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
39#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
40#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
41#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
42#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
43#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
44#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
45#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
46#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
47
48#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
49#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
50#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
51#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
52#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
53#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
54#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
55#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
56#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
57
58#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
59
60#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
61
62
63#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
64
65
66#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
67
68
69#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
70
71
72#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
73
74#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
75#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
76#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
77#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
78
79#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
80#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
81#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
82#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
83#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
84
85#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
86#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
87#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
88#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
89
90#ifdef __ASSEMBLY__
91
92 .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
93 ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
94 ldr \rd, [\ra]
95 and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
96 orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
97 str \rd, [\ra]
98 .endm
99
100#else
101
102#include <linux/types.h>
103#include <linux/io.h>
104
105static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
106 unsigned mux_bits, unsigned reg_stride)
107{
108 unsigned shift = pin * mux_bits % 32;
109 unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
110 u32 mask = (1U << mux_bits) - 1;
111 u32 tmp;
112
113 tmp = readl(reg);
114 tmp &= ~(mask << shift);
115 tmp |= (mask & muxval) << shift;
116 writel(tmp, reg);
117}
118
119static inline void sg_set_iectrl(unsigned pin)
120{
121 unsigned bit = pin % 32;
122 unsigned long reg = SG_IECTRL + pin / 32 * 4;
123 u32 tmp;
124
125 tmp = readl(reg);
126 tmp |= 1 << bit;
127 writel(tmp, reg);
128}
129
130static inline void sg_set_iectrl_range(unsigned min, unsigned max)
131{
132 int i;
133
134 for (i = min; i <= max; i++)
135 sg_set_iectrl(i);
136}
137
138#endif
139
140#endif
141
