LXR uboot/arch/powerpc/include/asm/cpm

   1/*
   2 * MPC8260 Communication Processor Module.
   3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
   4 *
   5 * This file contains structures and information for the communication
   6 * processor channels found in the dual port RAM or parameter RAM.
   7 * All CPM control and status is available through the MPC8260 internal
   8 * memory map.  See immap.h for details.
   9 */
  10#ifndef __CPM_82XX__
  11#define __CPM_82XX__
  12
  13#include <asm/immap_8260.h>
  14
  15/* CPM Command register.
  16*/
  17#define CPM_CR_RST      ((uint)0x80000000)
  18#define CPM_CR_PAGE     ((uint)0x7c000000)
  19#define CPM_CR_SBLOCK   ((uint)0x03e00000)
  20#define CPM_CR_FLG      ((uint)0x00010000)
  21#define CPM_CR_MCN      ((uint)0x00003fc0)
  22#define CPM_CR_OPCODE   ((uint)0x0000000f)
  23
  24/* Device sub-block and page codes.
  25*/
  26#define CPM_CR_SCC1_SBLOCK      (0x04)
  27#define CPM_CR_SCC2_SBLOCK      (0x05)
  28#define CPM_CR_SCC3_SBLOCK      (0x06)
  29#define CPM_CR_SCC4_SBLOCK      (0x07)
  30#define CPM_CR_SMC1_SBLOCK      (0x08)
  31#define CPM_CR_SMC2_SBLOCK      (0x09)
  32#define CPM_CR_SPI_SBLOCK       (0x0a)
  33#define CPM_CR_I2C_SBLOCK       (0x0b)
  34#define CPM_CR_TIMER_SBLOCK     (0x0f)
  35#define CPM_CR_RAND_SBLOCK      (0x0e)
  36#define CPM_CR_FCC1_SBLOCK      (0x10)
  37#define CPM_CR_FCC2_SBLOCK      (0x11)
  38#define CPM_CR_FCC3_SBLOCK      (0x12)
  39#define CPM_CR_IDMA1_SBLOCK     (0x14)
  40#define CPM_CR_IDMA2_SBLOCK     (0x15)
  41#define CPM_CR_IDMA3_SBLOCK     (0x16)
  42#define CPM_CR_IDMA4_SBLOCK     (0x17)
  43#define CPM_CR_MCC1_SBLOCK      (0x1c)
  44
  45#define CPM_CR_SCC1_PAGE        (0x00)
  46#define CPM_CR_SCC2_PAGE        (0x01)
  47#define CPM_CR_SCC3_PAGE        (0x02)
  48#define CPM_CR_SCC4_PAGE        (0x03)
  49#define CPM_CR_SMC1_PAGE        (0x07)
  50#define CPM_CR_SMC2_PAGE        (0x08)
  51#define CPM_CR_SPI_PAGE         (0x09)
  52#define CPM_CR_I2C_PAGE         (0x0a)
  53#define CPM_CR_TIMER_PAGE       (0x0a)
  54#define CPM_CR_RAND_PAGE        (0x0a)
  55#define CPM_CR_FCC1_PAGE        (0x04)
  56#define CPM_CR_FCC2_PAGE        (0x05)
  57#define CPM_CR_FCC3_PAGE        (0x06)
  58#define CPM_CR_IDMA1_PAGE       (0x07)
  59#define CPM_CR_IDMA2_PAGE       (0x08)
  60#define CPM_CR_IDMA3_PAGE       (0x09)
  61#define CPM_CR_IDMA4_PAGE       (0x0a)
  62#define CPM_CR_MCC1_PAGE        (0x07)
  63#define CPM_CR_MCC2_PAGE        (0x08)
  64
  65/* Some opcodes (there are more...later)
  66*/
  67#define CPM_CR_INIT_TRX         ((ushort)0x0000)
  68#define CPM_CR_INIT_RX          ((ushort)0x0001)
  69#define CPM_CR_INIT_TX          ((ushort)0x0002)
  70#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  71#define CPM_CR_STOP_TX          ((ushort)0x0004)
  72#define CPM_CR_RESTART_TX       ((ushort)0x0006)
  73#define CPM_CR_SET_GADDR        ((ushort)0x0008)
  74
  75#define mk_cr_cmd(PG, SBC, MCN, OP) \
  76        ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
  77
  78/* Dual Port RAM addresses.  The first 16K is available for almost
  79 * any CPM use, so we put the BDs there.  The first 128 bytes are
  80 * used for SMC1 and SMC2 parameter RAM, so we start allocating
  81 * BDs above that.  All of this must change when we start
  82 * downloading RAM microcode.
  83 */
  84#define CPM_DATAONLY_BASE       ((uint)128)
  85#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  86#ifndef CONFIG_MPC8272_FAMILY
  87#define CPM_DATAONLY_SIZE       ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
  88#define CPM_FCC_SPECIAL_BASE    ((uint)0x0000b000)
  89#else  /* 8247/48/71/72 */
  90#define CPM_DATAONLY_SIZE       ((uint)(4 * 1024) - CPM_DATAONLY_BASE)
  91#define CPM_FCC_SPECIAL_BASE    ((uint)0x00009000)
  92#endif /* !CONFIG_MPC8272_FAMILY */
  93
  94/* The number of pages of host memory we allocate for CPM.  This is
  95 * done early in kernel initialization to get physically contiguous
  96 * pages.
  97 */
  98#define NUM_CPM_HOST_PAGES      2
  99
 100
 101/* Export the base address of the communication processor registers
 102 * and dual port ram.
 103 */
 104extern  cpm8260_t       *cpmp;          /* Pointer to comm processor */
 105uint            m8260_cpm_dpalloc(uint size, uint align);
 106uint            m8260_cpm_hostalloc(uint size, uint align);
 107void            m8260_cpm_setbrg(uint brg, uint rate);
 108void            m8260_cpm_fastbrg(uint brg, uint rate, int div16);
 109void            m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
 110
 111/* Buffer descriptors used by many of the CPM protocols.
 112*/
 113typedef struct cpm_buf_desc {
 114        ushort  cbd_sc;         /* Status and Control */
 115        ushort  cbd_datlen;     /* Data length in buffer */
 116        uint    cbd_bufaddr;    /* Buffer address in host memory */
 117} cbd_t;
 118
 119#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
 120#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 121#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 122#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 123#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 124#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 125#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 126#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 127#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 128#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 129#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 130#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 131#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
 132
 133/* Function code bits, usually generic to devices.
 134*/
 135#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
 136#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
 137#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
 138#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
 139#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
 140
 141/* Parameter RAM offsets from the base.
 142*/
 143#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
 144#define CPM_POST_WORD_ADDR      0x80FC  /* steal a long at the end of SCC1 */
 145#else
 146#define CPM_POST_WORD_ADDR      CONFIG_SYS_CPM_POST_WORD_ADDR
 147#endif
 148
 149#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 150#define CPM_BOOTCOUNT_ADDR      (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
 151#else
 152#define CPM_BOOTCOUNT_ADDR      CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 153#endif
 154
 155#define PROFF_SCC1              ((uint)0x8000)
 156#define PROFF_SCC2              ((uint)0x8100)
 157#define PROFF_SCC3              ((uint)0x8200)
 158#define PROFF_SCC4              ((uint)0x8300)
 159#define PROFF_FCC1              ((uint)0x8400)
 160#define PROFF_FCC2              ((uint)0x8500)
 161#define PROFF_FCC3              ((uint)0x8600)
 162#define PROFF_MCC1              ((uint)0x8700)
 163#define PROFF_SMC1_BASE         ((uint)0x87fc)
 164#define PROFF_IDMA1_BASE        ((uint)0x87fe)
 165#define PROFF_MCC2              ((uint)0x8800)
 166#define PROFF_SMC2_BASE         ((uint)0x88fc)
 167#define PROFF_IDMA2_BASE        ((uint)0x88fe)
 168#define PROFF_SPI_BASE          ((uint)0x89fc)
 169#define PROFF_IDMA3_BASE        ((uint)0x89fe)
 170#define PROFF_TIMERS            ((uint)0x8ae0)
 171#define PROFF_REVNUM            ((uint)0x8af0)
 172#define PROFF_RAND              ((uint)0x8af8)
 173#define PROFF_I2C_BASE          ((uint)0x8afc)
 174#define PROFF_IDMA4_BASE        ((uint)0x8afe)
 175
 176/* The SMCs are relocated to any of the first eight DPRAM pages.
 177 * We will fix these at the first locations of DPRAM, until we
 178 * get some microcode patches :-).
 179 * The parameter ram space for the SMCs is fifty-some bytes, and
 180 * they are required to start on a 64 byte boundary.
 181 */
 182#define PROFF_SMC1      (0)
 183#define PROFF_SMC2      (64)
 184#define PROFF_SPI       ((16*1024) - 128)
 185
 186/* Define enough so I can at least use the serial port as a UART.
 187 */
 188typedef struct smc_uart {
 189        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 190        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 191        u_char  smc_rfcr;       /* Rx function code */
 192        u_char  smc_tfcr;       /* Tx function code */
 193        ushort  smc_mrblr;      /* Max receive buffer length */
 194        uint    smc_rstate;     /* Internal */
 195        uint    smc_idp;        /* Internal */
 196        ushort  smc_rbptr;      /* Internal */
 197        ushort  smc_ibc;        /* Internal */
 198        uint    smc_rxtmp;      /* Internal */
 199        uint    smc_tstate;     /* Internal */
 200        uint    smc_tdp;        /* Internal */
 201        ushort  smc_tbptr;      /* Internal */
 202        ushort  smc_tbc;        /* Internal */
 203        uint    smc_txtmp;      /* Internal */
 204        ushort  smc_maxidl;     /* Maximum idle characters */
 205        ushort  smc_tmpidl;     /* Temporary idle counter */
 206        ushort  smc_brklen;     /* Last received break length */
 207        ushort  smc_brkec;      /* rcv'd break condition counter */
 208        ushort  smc_brkcr;      /* xmt break count register */
 209        ushort  smc_rmask;      /* Temporary bit mask */
 210        uint    smc_stmp;       /* SDMA Temp */
 211} smc_uart_t;
 212
 213/* SMC uart mode register (Internal memory map).
 214*/
 215#define SMCMR_REN       ((ushort)0x0001)
 216#define SMCMR_TEN       ((ushort)0x0002)
 217#define SMCMR_DM        ((ushort)0x000c)
 218#define SMCMR_SM_GCI    ((ushort)0x0000)
 219#define SMCMR_SM_UART   ((ushort)0x0020)
 220#define SMCMR_SM_TRANS  ((ushort)0x0030)
 221#define SMCMR_SM_MASK   ((ushort)0x0030)
 222#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 223#define SMCMR_REVD      SMCMR_PM_EVEN
 224#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 225#define SMCMR_BS        SMCMR_PEN
 226#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 227#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 228#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 229
 230/* SMC Event and Mask register.
 231*/
 232#define SMCM_TXE        ((unsigned char)0x10)
 233#define SMCM_BSY        ((unsigned char)0x04)
 234#define SMCM_TX         ((unsigned char)0x02)
 235#define SMCM_RX         ((unsigned char)0x01)
 236
 237/* Baud rate generators.
 238*/
 239#define CPM_BRG_RST             ((uint)0x00020000)
 240#define CPM_BRG_EN              ((uint)0x00010000)
 241#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 242#define CPM_BRG_EXTC_CLK3_9     ((uint)0x00004000)
 243#define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
 244#define CPM_BRG_ATB             ((uint)0x00002000)
 245#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 246#define CPM_BRG_DIV16           ((uint)0x00000001)
 247
 248/* SCCs.
 249*/
 250#define SCC_GSMRH_IRP           ((uint)0x00040000)
 251#define SCC_GSMRH_GDE           ((uint)0x00010000)
 252#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 253#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 254#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 255#define SCC_GSMRH_REVD          ((uint)0x00002000)
 256#define SCC_GSMRH_TRX           ((uint)0x00001000)
 257#define SCC_GSMRH_TTX           ((uint)0x00000800)
 258#define SCC_GSMRH_CDP           ((uint)0x00000400)
 259#define SCC_GSMRH_CTSP          ((uint)0x00000200)
 260#define SCC_GSMRH_CDS           ((uint)0x00000100)
 261#define SCC_GSMRH_CTSS          ((uint)0x00000080)
 262#define SCC_GSMRH_TFL           ((uint)0x00000040)
 263#define SCC_GSMRH_RFW           ((uint)0x00000020)
 264#define SCC_GSMRH_TXSY          ((uint)0x00000010)
 265#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 266#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 267#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 268#define SCC_GSMRH_RTSM          ((uint)0x00000002)
 269#define SCC_GSMRH_RSYN          ((uint)0x00000001)
 270
 271#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 272#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 273#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 274#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 275#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 276#define SCC_GSMRL_TCI           ((uint)0x10000000)
 277#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 278#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 279#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 280#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 281#define SCC_GSMRL_RINV          ((uint)0x02000000)
 282#define SCC_GSMRL_TINV          ((uint)0x01000000)
 283#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 284#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 285#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 286#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 287#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 288#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 289#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 290#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 291#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 292#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 293#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 294#define SCC_GSMRL_TEND          ((uint)0x00040000)
 295#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 296#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 297#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 298#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 299#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 300#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 301#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 302#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 303#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 304#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 305#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 306#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 307#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 308#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 309#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 310#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 311#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 312#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 313#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 314#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 315#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 316#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 317#define SCC_GSMRL_ENR           ((uint)0x00000020)
 318#define SCC_GSMRL_ENT           ((uint)0x00000010)
 319#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 320#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 321#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 322#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 323#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 324#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 325#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 326#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 327#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 328#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 329
 330#define SCC_TODR_TOD            ((ushort)0x8000)
 331
 332/* SCC Event and Mask register.
 333*/
 334#define SCCM_TXE        ((unsigned char)0x10)
 335#define SCCM_BSY        ((unsigned char)0x04)
 336#define SCCM_TX         ((unsigned char)0x02)
 337#define SCCM_RX         ((unsigned char)0x01)
 338
 339typedef struct scc_param {
 340        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 341        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 342        u_char  scc_rfcr;       /* Rx function code */
 343        u_char  scc_tfcr;       /* Tx function code */
 344        ushort  scc_mrblr;      /* Max receive buffer length */
 345        uint    scc_rstate;     /* Internal */
 346        uint    scc_idp;        /* Internal */
 347        ushort  scc_rbptr;      /* Internal */
 348        ushort  scc_ibc;        /* Internal */
 349        uint    scc_rxtmp;      /* Internal */
 350        uint    scc_tstate;     /* Internal */
 351        uint    scc_tdp;        /* Internal */
 352        ushort  scc_tbptr;      /* Internal */
 353        ushort  scc_tbc;        /* Internal */
 354        uint    scc_txtmp;      /* Internal */
 355        uint    scc_rcrc;       /* Internal */
 356        uint    scc_tcrc;       /* Internal */
 357} sccp_t;
 358
 359/* CPM Ethernet through SCC1.
 360 */
 361typedef struct scc_enet {
 362        sccp_t  sen_genscc;
 363        uint    sen_cpres;      /* Preset CRC */
 364        uint    sen_cmask;      /* Constant mask for CRC */
 365        uint    sen_crcec;      /* CRC Error counter */
 366        uint    sen_alec;       /* alignment error counter */
 367        uint    sen_disfc;      /* discard frame counter */
 368        ushort  sen_pads;       /* Tx short frame pad character */
 369        ushort  sen_retlim;     /* Retry limit threshold */
 370        ushort  sen_retcnt;     /* Retry limit counter */
 371        ushort  sen_maxflr;     /* maximum frame length register */
 372        ushort  sen_minflr;     /* minimum frame length register */
 373        ushort  sen_maxd1;      /* maximum DMA1 length */
 374        ushort  sen_maxd2;      /* maximum DMA2 length */
 375        ushort  sen_maxd;       /* Rx max DMA */
 376        ushort  sen_dmacnt;     /* Rx DMA counter */
 377        ushort  sen_maxb;       /* Max BD byte count */
 378        ushort  sen_gaddr1;     /* Group address filter */
 379        ushort  sen_gaddr2;
 380        ushort  sen_gaddr3;
 381        ushort  sen_gaddr4;
 382        uint    sen_tbuf0data0; /* Save area 0 - current frame */
 383        uint    sen_tbuf0data1; /* Save area 1 - current frame */
 384        uint    sen_tbuf0rba;   /* Internal */
 385        uint    sen_tbuf0crc;   /* Internal */
 386        ushort  sen_tbuf0bcnt;  /* Internal */
 387        ushort  sen_paddrh;     /* physical address (MSB) */
 388        ushort  sen_paddrm;
 389        ushort  sen_paddrl;     /* physical address (LSB) */
 390        ushort  sen_pper;       /* persistence */
 391        ushort  sen_rfbdptr;    /* Rx first BD pointer */
 392        ushort  sen_tfbdptr;    /* Tx first BD pointer */
 393        ushort  sen_tlbdptr;    /* Tx last BD pointer */
 394        uint    sen_tbuf1data0; /* Save area 0 - current frame */
 395        uint    sen_tbuf1data1; /* Save area 1 - current frame */
 396        uint    sen_tbuf1rba;   /* Internal */
 397        uint    sen_tbuf1crc;   /* Internal */
 398        ushort  sen_tbuf1bcnt;  /* Internal */
 399        ushort  sen_txlen;      /* Tx Frame length counter */
 400        ushort  sen_iaddr1;     /* Individual address filter */
 401        ushort  sen_iaddr2;
 402        ushort  sen_iaddr3;
 403        ushort  sen_iaddr4;
 404        ushort  sen_boffcnt;    /* Backoff counter */
 405
 406        /* NOTE: Some versions of the manual have the following items
 407         * incorrectly documented.  Below is the proper order.
 408         */
 409        ushort  sen_taddrh;     /* temp address (MSB) */
 410        ushort  sen_taddrm;
 411        ushort  sen_taddrl;     /* temp address (LSB) */
 412} scc_enet_t;
 413
 414
 415/* SCC Event register as used by Ethernet.
 416*/
 417#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 418#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 419#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 420#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 421#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 422#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 423
 424/* SCC Mode Register (PSMR) as used by Ethernet.
 425*/
 426#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 427#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 428#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 429#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 430#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 431#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 432#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 433#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 434#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 435#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 436#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 437#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 438#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 439
 440/* Buffer descriptor control/status used by Ethernet receive.
 441 * Common to SCC and FCC.
 442 */
 443#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 444#define BD_ENET_RX_WRAP         ((ushort)0x2000)
 445#define BD_ENET_RX_INTR         ((ushort)0x1000)
 446#define BD_ENET_RX_LAST         ((ushort)0x0800)
 447#define BD_ENET_RX_FIRST        ((ushort)0x0400)
 448#define BD_ENET_RX_MISS         ((ushort)0x0100)
 449#define BD_ENET_RX_BC           ((ushort)0x0080)        /* FCC Only */
 450#define BD_ENET_RX_MC           ((ushort)0x0040)        /* FCC Only */
 451#define BD_ENET_RX_LG           ((ushort)0x0020)
 452#define BD_ENET_RX_NO           ((ushort)0x0010)
 453#define BD_ENET_RX_SH           ((ushort)0x0008)
 454#define BD_ENET_RX_CR           ((ushort)0x0004)
 455#define BD_ENET_RX_OV           ((ushort)0x0002)
 456#define BD_ENET_RX_CL           ((ushort)0x0001)
 457#define BD_ENET_RX_STATS        ((ushort)0x01ff)        /* All status bits */
 458
 459/* Buffer descriptor control/status used by Ethernet transmit.
 460 * Common to SCC and FCC.
 461 */
 462#define BD_ENET_TX_READY        ((ushort)0x8000)
 463#define BD_ENET_TX_PAD          ((ushort)0x4000)
 464#define BD_ENET_TX_WRAP         ((ushort)0x2000)
 465#define BD_ENET_TX_INTR         ((ushort)0x1000)
 466#define BD_ENET_TX_LAST         ((ushort)0x0800)
 467#define BD_ENET_TX_TC           ((ushort)0x0400)
 468#define BD_ENET_TX_DEF          ((ushort)0x0200)
 469#define BD_ENET_TX_HB           ((ushort)0x0100)
 470#define BD_ENET_TX_LC           ((ushort)0x0080)
 471#define BD_ENET_TX_RL           ((ushort)0x0040)
 472#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
 473#define BD_ENET_TX_UN           ((ushort)0x0002)
 474#define BD_ENET_TX_CSL          ((ushort)0x0001)
 475#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 476
 477/* SCC as UART
 478*/
 479typedef struct scc_uart {
 480        sccp_t  scc_genscc;
 481        uint    scc_res1;       /* Reserved */
 482        uint    scc_res2;       /* Reserved */
 483        ushort  scc_maxidl;     /* Maximum idle chars */
 484        ushort  scc_idlc;       /* temp idle counter */
 485        ushort  scc_brkcr;      /* Break count register */
 486        ushort  scc_parec;      /* receive parity error counter */
 487        ushort  scc_frmec;      /* receive framing error counter */
 488        ushort  scc_nosec;      /* receive noise counter */
 489        ushort  scc_brkec;      /* receive break condition counter */
 490        ushort  scc_brkln;      /* last received break length */
 491        ushort  scc_uaddr1;     /* UART address character 1 */
 492        ushort  scc_uaddr2;     /* UART address character 2 */
 493        ushort  scc_rtemp;      /* Temp storage */
 494        ushort  scc_toseq;      /* Transmit out of sequence char */
 495        ushort  scc_char1;      /* control character 1 */
 496        ushort  scc_char2;      /* control character 2 */
 497        ushort  scc_char3;      /* control character 3 */
 498        ushort  scc_char4;      /* control character 4 */
 499        ushort  scc_char5;      /* control character 5 */
 500        ushort  scc_char6;      /* control character 6 */
 501        ushort  scc_char7;      /* control character 7 */
 502        ushort  scc_char8;      /* control character 8 */
 503        ushort  scc_rccm;       /* receive control character mask */
 504        ushort  scc_rccr;       /* receive control character register */
 505        ushort  scc_rlbc;       /* receive last break character */
 506} scc_uart_t;
 507
 508/* SCC Event and Mask registers when it is used as a UART.
 509*/
 510#define UART_SCCM_GLR           ((ushort)0x1000)
 511#define UART_SCCM_GLT           ((ushort)0x0800)
 512#define UART_SCCM_AB            ((ushort)0x0200)
 513#define UART_SCCM_IDL           ((ushort)0x0100)
 514#define UART_SCCM_GRA           ((ushort)0x0080)
 515#define UART_SCCM_BRKE          ((ushort)0x0040)
 516#define UART_SCCM_BRKS          ((ushort)0x0020)
 517#define UART_SCCM_CCR           ((ushort)0x0008)
 518#define UART_SCCM_BSY           ((ushort)0x0004)
 519#define UART_SCCM_TX            ((ushort)0x0002)
 520#define UART_SCCM_RX            ((ushort)0x0001)
 521
 522/* The SCC PSMR when used as a UART.
 523*/
 524#define SCU_PSMR_FLC            ((ushort)0x8000)
 525#define SCU_PSMR_SL             ((ushort)0x4000)
 526#define SCU_PSMR_CL             ((ushort)0x3000)
 527#define SCU_PSMR_UM             ((ushort)0x0c00)
 528#define SCU_PSMR_FRZ            ((ushort)0x0200)
 529#define SCU_PSMR_RZS            ((ushort)0x0100)
 530#define SCU_PSMR_SYN            ((ushort)0x0080)
 531#define SCU_PSMR_DRT            ((ushort)0x0040)
 532#define SCU_PSMR_PEN            ((ushort)0x0010)
 533#define SCU_PSMR_RPM            ((ushort)0x000c)
 534#define SCU_PSMR_REVP           ((ushort)0x0008)
 535#define SCU_PSMR_TPM            ((ushort)0x0003)
 536#define SCU_PSMR_TEVP           ((ushort)0x0003)
 537
 538/* CPM Transparent mode SCC.
 539 */
 540typedef struct scc_trans {
 541        sccp_t  st_genscc;
 542        uint    st_cpres;       /* Preset CRC */
 543        uint    st_cmask;       /* Constant mask for CRC */
 544} scc_trans_t;
 545
 546#define BD_SCC_TX_LAST          ((ushort)0x0800)
 547
 548/*  SCC as HDLC controller - taken from commproc.h
 549 */
 550typedef struct scc_hdlc {
 551        sccp_t  sh_genscc;
 552        /*
 553        * HDLC specific parameter RAM
 554        */
 555        uchar   res[4];         /* reserved */
 556        ulong   sh_cmask;       /* CRC constant */
 557        ulong   sh_cpres;       /* CRC preset */
 558        ushort  sh_disfc;       /* discarded frame counter */
 559        ushort  sh_crcec;       /* CRC error counter */
 560        ushort  sh_abtsc;       /* abort sequence counter */
 561        ushort  sh_nmarc;       /* nonmatching address rx cnt */
 562        ushort  sh_retrc;       /* frame retransmission cnt */
 563        ushort  sh_mflr;        /* maximum frame length reg */
 564        ushort  sh_maxcnt;      /* maximum length counter */
 565        ushort  sh_rfthr;       /* received frames threshold */
 566        ushort  sh_rfcnt;       /* received frames count */
 567        ushort  sh_hmask;       /* user defined frm addr mask */
 568        ushort  sh_haddr1;      /* user defined frm address 1 */
 569        ushort  sh_haddr2;      /* user defined frm address 2 */
 570        ushort  sh_haddr3;      /* user defined frm address 3 */
 571        ushort  sh_haddr4;      /* user defined frm address 4 */
 572        ushort  tmp;            /* temp */
 573        ushort  tmp_mb;         /* temp */
 574} scc_hdlc_t;
 575
 576/* How about some FCCs.....
 577*/
 578#define FCC_GFMR_DIAG_NORM      ((uint)0x00000000)
 579#define FCC_GFMR_DIAG_LE        ((uint)0x40000000)
 580#define FCC_GFMR_DIAG_AE        ((uint)0x80000000)
 581#define FCC_GFMR_DIAG_ALE       ((uint)0xc0000000)
 582#define FCC_GFMR_TCI            ((uint)0x20000000)
 583#define FCC_GFMR_TRX            ((uint)0x10000000)
 584#define FCC_GFMR_TTX            ((uint)0x08000000)
 585#define FCC_GFMR_TTX            ((uint)0x08000000)
 586#define FCC_GFMR_CDP            ((uint)0x04000000)
 587#define FCC_GFMR_CTSP           ((uint)0x02000000)
 588#define FCC_GFMR_CDS            ((uint)0x01000000)
 589#define FCC_GFMR_CTSS           ((uint)0x00800000)
 590#define FCC_GFMR_SYNL_NONE      ((uint)0x00000000)
 591#define FCC_GFMR_SYNL_AUTO      ((uint)0x00004000)
 592#define FCC_GFMR_SYNL_8         ((uint)0x00008000)
 593#define FCC_GFMR_SYNL_16        ((uint)0x0000c000)
 594#define FCC_GFMR_RTSM           ((uint)0x00002000)
 595#define FCC_GFMR_RENC_NRZ       ((uint)0x00000000)
 596#define FCC_GFMR_RENC_NRZI      ((uint)0x00000800)
 597#define FCC_GFMR_REVD           ((uint)0x00000400)
 598#define FCC_GFMR_TENC_NRZ       ((uint)0x00000000)
 599#define FCC_GFMR_TENC_NRZI      ((uint)0x00000100)
 600#define FCC_GFMR_TCRC_16        ((uint)0x00000000)
 601#define FCC_GFMR_TCRC_32        ((uint)0x00000080)
 602#define FCC_GFMR_ENR            ((uint)0x00000020)
 603#define FCC_GFMR_ENT            ((uint)0x00000010)
 604#define FCC_GFMR_MODE_ENET      ((uint)0x0000000c)
 605#define FCC_GFMR_MODE_ATM       ((uint)0x0000000a)
 606#define FCC_GFMR_MODE_HDLC      ((uint)0x00000000)
 607
 608/* Generic FCC parameter ram.
 609*/
 610typedef struct fcc_param {
 611        ushort  fcc_riptr;      /* Rx Internal temp pointer */
 612        ushort  fcc_tiptr;      /* Tx Internal temp pointer */
 613        ushort  fcc_res1;
 614        ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
 615        uint    fcc_rstate;     /* Upper byte is Func code, must be set */
 616        uint    fcc_rbase;      /* Receive BD base */
 617        ushort  fcc_rbdstat;    /* RxBD status */
 618        ushort  fcc_rbdlen;     /* RxBD down counter */
 619        uint    fcc_rdptr;      /* RxBD internal data pointer */
 620        uint    fcc_tstate;     /* Upper byte is Func code, must be set */
 621        uint    fcc_tbase;      /* Transmit BD base */
 622        ushort  fcc_tbdstat;    /* TxBD status */
 623        ushort  fcc_tbdlen;     /* TxBD down counter */
 624        uint    fcc_tdptr;      /* TxBD internal data pointer */
 625        uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
 626        uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
 627        uint    fcc_rcrc;       /* Rx temp CRC */
 628        uint    fcc_res2;
 629        uint    fcc_tcrc;       /* Tx temp CRC */
 630} fccp_t;
 631
 632
 633/* Ethernet controller through FCC.
 634*/
 635typedef struct fcc_enet {
 636        fccp_t  fen_genfcc;
 637        uint    fen_statbuf;    /* Internal status buffer */
 638        uint    fen_camptr;     /* CAM address */
 639        uint    fen_cmask;      /* Constant mask for CRC */
 640        uint    fen_cpres;      /* Preset CRC */
 641        uint    fen_crcec;      /* CRC Error counter */
 642        uint    fen_alec;       /* alignment error counter */
 643        uint    fen_disfc;      /* discard frame counter */
 644        ushort  fen_retlim;     /* Retry limit */
 645        ushort  fen_retcnt;     /* Retry counter */
 646        ushort  fen_pper;       /* Persistence */
 647        ushort  fen_boffcnt;    /* backoff counter */
 648        uint    fen_gaddrh;     /* Group address filter, high 32-bits */
 649        uint    fen_gaddrl;     /* Group address filter, low 32-bits */
 650        ushort  fen_tfcstat;    /* out of sequence TxBD */
 651        ushort  fen_tfclen;
 652        uint    fen_tfcptr;
 653        ushort  fen_mflr;       /* Maximum frame length (1518) */
 654        ushort  fen_paddrh;     /* MAC address */
 655        ushort  fen_paddrm;
 656        ushort  fen_paddrl;
 657        ushort  fen_ibdcount;   /* Internal BD counter */
 658        ushort  fen_idbstart;   /* Internal BD start pointer */
 659        ushort  fen_ibdend;     /* Internal BD end pointer */
 660        ushort  fen_txlen;      /* Internal Tx frame length counter */
 661        uint    fen_ibdbase[8]; /* Internal use */
 662        uint    fen_iaddrh;     /* Individual address filter */
 663        uint    fen_iaddrl;
 664        ushort  fen_minflr;     /* Minimum frame length (64) */
 665        ushort  fen_taddrh;     /* Filter transfer MAC address */
 666        ushort  fen_taddrm;
 667        ushort  fen_taddrl;
 668        ushort  fen_padptr;     /* Pointer to pad byte buffer */
 669        ushort  fen_cftype;     /* control frame type */
 670        ushort  fen_cfrange;    /* control frame range */
 671        ushort  fen_maxb;       /* maximum BD count */
 672        ushort  fen_maxd1;      /* Max DMA1 length (1520) */
 673        ushort  fen_maxd2;      /* Max DMA2 length (1520) */
 674        ushort  fen_maxd;       /* internal max DMA count */
 675        ushort  fen_dmacnt;     /* internal DMA counter */
 676        uint    fen_octc;       /* Total octect counter */
 677        uint    fen_colc;       /* Total collision counter */
 678        uint    fen_broc;       /* Total broadcast packet counter */
 679        uint    fen_mulc;       /* Total multicast packet count */
 680        uint    fen_uspc;       /* Total packets < 64 bytes */
 681        uint    fen_frgc;       /* Total packets < 64 bytes with errors */
 682        uint    fen_ospc;       /* Total packets > 1518 */
 683        uint    fen_jbrc;       /* Total packets > 1518 with errors */
 684        uint    fen_p64c;       /* Total packets == 64 bytes */
 685        uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
 686        uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
 687        uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
 688        uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
 689        uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
 690        uint    fen_cambuf;     /* Internal CAM buffer poiner */
 691        ushort  fen_rfthr;      /* Received frames threshold */
 692        ushort  fen_rfcnt;      /* Received frames count */
 693} fcc_enet_t;
 694
 695/* FCC Event/Mask register as used by Ethernet.
 696*/
 697#define FCC_ENET_GRA    ((ushort)0x0080)        /* Graceful stop complete */
 698#define FCC_ENET_RXC    ((ushort)0x0040)        /* Control Frame Received */
 699#define FCC_ENET_TXC    ((ushort)0x0020)        /* Out of seq. Tx sent */
 700#define FCC_ENET_TXE    ((ushort)0x0010)        /* Transmit Error */
 701#define FCC_ENET_RXF    ((ushort)0x0008)        /* Full frame received */
 702#define FCC_ENET_BSY    ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
 703#define FCC_ENET_TXB    ((ushort)0x0002)        /* A buffer was transmitted */
 704#define FCC_ENET_RXB    ((ushort)0x0001)        /* A buffer was received */
 705
 706/* FCC Mode Register (FPSMR) as used by Ethernet.
 707*/
 708#define FCC_PSMR_HBC    ((uint)0x80000000)      /* Enable heartbeat */
 709#define FCC_PSMR_FC     ((uint)0x40000000)      /* Force Collision */
 710#define FCC_PSMR_SBT    ((uint)0x20000000)      /* Stop backoff timer */
 711#define FCC_PSMR_LPB    ((uint)0x10000000)      /* Local protect. 1 = FDX */
 712#define FCC_PSMR_LCW    ((uint)0x08000000)      /* Late collision select */
 713#define FCC_PSMR_FDE    ((uint)0x04000000)      /* Full Duplex Enable */
 714#define FCC_PSMR_MON    ((uint)0x02000000)      /* RMON Enable */
 715#define FCC_PSMR_PRO    ((uint)0x00400000)      /* Promiscuous Enable */
 716#define FCC_PSMR_FCE    ((uint)0x00200000)      /* Flow Control Enable */
 717#define FCC_PSMR_RSH    ((uint)0x00100000)      /* Receive Short Frames */
 718#define FCC_PSMR_RMII   ((uint)0x00020000)      /* Use RMII interface */
 719#define FCC_PSMR_CAM    ((uint)0x00000400)      /* CAM enable */
 720#define FCC_PSMR_BRO    ((uint)0x00000200)      /* Broadcast pkt discard */
 721#define FCC_PSMR_ENCRC  ((uint)0x00000080)      /* Use 32-bit CRC */
 722
 723/* IIC parameter RAM.
 724*/
 725typedef struct iic {
 726        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 727        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 728        u_char  iic_rfcr;       /* Rx function code */
 729        u_char  iic_tfcr;       /* Tx function code */
 730        ushort  iic_mrblr;      /* Max receive buffer length */
 731        uint    iic_rstate;     /* Internal */
 732        uint    iic_rdp;        /* Internal */
 733        ushort  iic_rbptr;      /* Internal */
 734        ushort  iic_rbc;        /* Internal */
 735        uint    iic_rxtmp;      /* Internal */
 736        uint    iic_tstate;     /* Internal */
 737        uint    iic_tdp;        /* Internal */
 738        ushort  iic_tbptr;      /* Internal */
 739        ushort  iic_tbc;        /* Internal */
 740        uint    iic_txtmp;      /* Internal */
 741} iic_t;
 742
 743/* SPI parameter RAM.
 744*/
 745typedef struct spi {
 746        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 747        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 748        u_char  spi_rfcr;       /* Rx function code */
 749        u_char  spi_tfcr;       /* Tx function code */
 750        ushort  spi_mrblr;      /* Max receive buffer length */
 751        uint    spi_rstate;     /* Internal */
 752        uint    spi_rdp;        /* Internal */
 753        ushort  spi_rbptr;      /* Internal */
 754        ushort  spi_rbc;        /* Internal */
 755        uint    spi_rxtmp;      /* Internal */
 756        uint    spi_tstate;     /* Internal */
 757        uint    spi_tdp;        /* Internal */
 758        ushort  spi_tbptr;      /* Internal */
 759        ushort  spi_tbc;        /* Internal */
 760        uint    spi_txtmp;      /* Internal */
 761        uint    spi_res;        /* Tx temp. */
 762        uint    spi_res1[4];    /* SDMA temp. */
 763} spi_t;
 764
 765/* SPI Mode register.
 766*/
 767#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 768#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 769#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 770#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 771#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 772#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 773#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 774#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 775#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 776
 777#define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
 778#define SPMODE_PM(x)    ((x) &0xF)
 779
 780/* SPI Event/Mask register.
 781*/
 782#define SPI_EMASK               0x37    /* Event Mask                           */
 783#define SPI_MME                 0x20    /* Multi-Master Error                   */
 784#define SPI_TXE                 0x10    /* Transmit Error                       */
 785#define SPI_BSY                 0x04    /* Busy                                 */
 786#define SPI_TXB                 0x02    /* Tx Buffer Empty                      */
 787#define SPI_RXB                 0x01    /* RX Buffer full/closed                */
 788
 789#define SPI_STR                 0x80    /* SPCOM: Start transmit                */
 790
 791#define SPI_EB          ((u_char)0x10)          /* big endian byte order */
 792
 793#define BD_IIC_START            ((ushort)0x0400)
 794
 795#endif /* __CPM_82XX__ */
 796