LXR uboot/arch/powerpc/include/asm/fsl

   1/*
   2 * Copyright 2010 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __FSL_SERDES_H
   8#define __FSL_SERDES_H
   9
  10#include <config.h>
  11
  12enum srds_prtcl {
  13        NONE = 0,
  14        PCIE1,
  15        PCIE2,
  16        PCIE3,
  17        PCIE4,
  18        SATA1,
  19        SATA2,
  20        SRIO1,
  21        SRIO2,
  22        SGMII_FM1_DTSEC1,
  23        SGMII_FM1_DTSEC2,
  24        SGMII_FM1_DTSEC3,
  25        SGMII_FM1_DTSEC4,
  26        SGMII_FM1_DTSEC5,
  27        SGMII_FM1_DTSEC6,
  28        SGMII_FM1_DTSEC9,
  29        SGMII_FM1_DTSEC10,
  30        SGMII_FM2_DTSEC1,
  31        SGMII_FM2_DTSEC2,
  32        SGMII_FM2_DTSEC3,
  33        SGMII_FM2_DTSEC4,
  34        SGMII_FM2_DTSEC5,
  35        SGMII_FM2_DTSEC6,
  36        SGMII_FM2_DTSEC9,
  37        SGMII_FM2_DTSEC10,
  38        SGMII_TSEC1,
  39        SGMII_TSEC2,
  40        SGMII_TSEC3,
  41        SGMII_TSEC4,
  42        XAUI_FM1,
  43        XAUI_FM2,
  44        AURORA,
  45        CPRI1,
  46        CPRI2,
  47        CPRI3,
  48        CPRI4,
  49        CPRI5,
  50        CPRI6,
  51        CPRI7,
  52        CPRI8,
  53        XAUI_FM1_MAC9,
  54        XAUI_FM1_MAC10,
  55        XAUI_FM2_MAC9,
  56        XAUI_FM2_MAC10,
  57        HIGIG_FM1_MAC9,
  58        HIGIG_FM1_MAC10,
  59        HIGIG_FM2_MAC9,
  60        HIGIG_FM2_MAC10,
  61        QSGMII_FM1_A,           /* A indicates MACs 1-4 */
  62        QSGMII_FM1_B,           /* B indicates MACs 5,6,9,10 */
  63        QSGMII_FM2_A,
  64        QSGMII_FM2_B,
  65        XFI_FM1_MAC1,
  66        XFI_FM1_MAC2,
  67        XFI_FM1_MAC9,
  68        XFI_FM1_MAC10,
  69        XFI_FM2_MAC9,
  70        XFI_FM2_MAC10,
  71        INTERLAKEN,
  72        QSGMII_SW1_A,           /* Indicates ports on L2 Switch */
  73        QSGMII_SW1_B,
  74        SGMII_2500_FM1_DTSEC1,
  75        SGMII_2500_FM1_DTSEC2,
  76        SGMII_2500_FM1_DTSEC3,
  77        SGMII_2500_FM1_DTSEC4,
  78        SGMII_2500_FM1_DTSEC5,
  79        SGMII_2500_FM1_DTSEC6,
  80        SGMII_2500_FM1_DTSEC9,
  81        SGMII_2500_FM1_DTSEC10,
  82        SGMII_2500_FM2_DTSEC1,
  83        SGMII_2500_FM2_DTSEC2,
  84        SGMII_2500_FM2_DTSEC3,
  85        SGMII_2500_FM2_DTSEC4,
  86        SGMII_2500_FM2_DTSEC5,
  87        SGMII_2500_FM2_DTSEC6,
  88        SGMII_2500_FM2_DTSEC9,
  89        SGMII_2500_FM2_DTSEC10,
  90        SGMII_SW1_MAC1,
  91        SGMII_SW1_MAC2,
  92        SGMII_SW1_MAC3,
  93        SGMII_SW1_MAC4,
  94        SGMII_SW1_MAC5,
  95        SGMII_SW1_MAC6,
  96        SERDES_PRCTL_COUNT      /* Keep this item the last one */
  97};
  98
  99enum srds {
 100        FSL_SRDS_1  = 0,
 101        FSL_SRDS_2  = 1,
 102        FSL_SRDS_3  = 2,
 103        FSL_SRDS_4  = 3,
 104};
 105
 106int is_serdes_configured(enum srds_prtcl device);
 107void fsl_serdes_init(void);
 108const char *serdes_clock_to_string(u32 clock);
 109
 110#ifdef CONFIG_FSL_CORENET
 111#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 112int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 113enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 114#else
 115int serdes_get_first_lane(enum srds_prtcl device);
 116#endif
 117#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
 118void serdes_reset_rx(enum srds_prtcl device);
 119#endif
 120#endif
 121
 122#endif /* __FSL_SERDES_H */
 123