LXR uboot/arch/x86/cpu/ivybridge/gma.c

   1/*
   2 * From Coreboot file of the same name
   3 *
   4 * Copyright (C) 2011 Chromium OS Authors
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0
   7 */
   8
   9#include <common.h>
  10#include <bios_emul.h>
  11#include <dm.h>
  12#include <errno.h>
  13#include <fdtdec.h>
  14#include <pci_rom.h>
  15#include <asm/intel_regs.h>
  16#include <asm/io.h>
  17#include <asm/mtrr.h>
  18#include <asm/pci.h>
  19#include <asm/arch/pch.h>
  20#include <asm/arch/sandybridge.h>
  21
  22struct gt_powermeter {
  23        u16 reg;
  24        u32 value;
  25};
  26
  27static const struct gt_powermeter snb_pm_gt1[] = {
  28        { 0xa200, 0xcc000000 },
  29        { 0xa204, 0x07000040 },
  30        { 0xa208, 0x0000fe00 },
  31        { 0xa20c, 0x00000000 },
  32        { 0xa210, 0x17000000 },
  33        { 0xa214, 0x00000021 },
  34        { 0xa218, 0x0817fe19 },
  35        { 0xa21c, 0x00000000 },
  36        { 0xa220, 0x00000000 },
  37        { 0xa224, 0xcc000000 },
  38        { 0xa228, 0x07000040 },
  39        { 0xa22c, 0x0000fe00 },
  40        { 0xa230, 0x00000000 },
  41        { 0xa234, 0x17000000 },
  42        { 0xa238, 0x00000021 },
  43        { 0xa23c, 0x0817fe19 },
  44        { 0xa240, 0x00000000 },
  45        { 0xa244, 0x00000000 },
  46        { 0xa248, 0x8000421e },
  47        { 0 }
  48};
  49
  50static const struct gt_powermeter snb_pm_gt2[] = {
  51        { 0xa200, 0x330000a6 },
  52        { 0xa204, 0x402d0031 },
  53        { 0xa208, 0x00165f83 },
  54        { 0xa20c, 0xf1000000 },
  55        { 0xa210, 0x00000000 },
  56        { 0xa214, 0x00160016 },
  57        { 0xa218, 0x002a002b },
  58        { 0xa21c, 0x00000000 },
  59        { 0xa220, 0x00000000 },
  60        { 0xa224, 0x330000a6 },
  61        { 0xa228, 0x402d0031 },
  62        { 0xa22c, 0x00165f83 },
  63        { 0xa230, 0xf1000000 },
  64        { 0xa234, 0x00000000 },
  65        { 0xa238, 0x00160016 },
  66        { 0xa23c, 0x002a002b },
  67        { 0xa240, 0x00000000 },
  68        { 0xa244, 0x00000000 },
  69        { 0xa248, 0x8000421e },
  70        { 0 }
  71};
  72
  73static const struct gt_powermeter ivb_pm_gt1[] = {
  74        { 0xa800, 0x00000000 },
  75        { 0xa804, 0x00021c00 },
  76        { 0xa808, 0x00000403 },
  77        { 0xa80c, 0x02001700 },
  78        { 0xa810, 0x05000200 },
  79        { 0xa814, 0x00000000 },
  80        { 0xa818, 0x00690500 },
  81        { 0xa81c, 0x0000007f },
  82        { 0xa820, 0x01002501 },
  83        { 0xa824, 0x00000300 },
  84        { 0xa828, 0x01000331 },
  85        { 0xa82c, 0x0000000c },
  86        { 0xa830, 0x00010016 },
  87        { 0xa834, 0x01100101 },
  88        { 0xa838, 0x00010103 },
  89        { 0xa83c, 0x00041300 },
  90        { 0xa840, 0x00000b30 },
  91        { 0xa844, 0x00000000 },
  92        { 0xa848, 0x7f000000 },
  93        { 0xa84c, 0x05000008 },
  94        { 0xa850, 0x00000001 },
  95        { 0xa854, 0x00000004 },
  96        { 0xa858, 0x00000007 },
  97        { 0xa85c, 0x00000000 },
  98        { 0xa860, 0x00010000 },
  99        { 0xa248, 0x0000221e },
 100        { 0xa900, 0x00000000 },
 101        { 0xa904, 0x00001c00 },
 102        { 0xa908, 0x00000000 },
 103        { 0xa90c, 0x06000000 },
 104        { 0xa910, 0x09000200 },
 105        { 0xa914, 0x00000000 },
 106        { 0xa918, 0x00590000 },
 107        { 0xa91c, 0x00000000 },
 108        { 0xa920, 0x04002501 },
 109        { 0xa924, 0x00000100 },
 110        { 0xa928, 0x03000410 },
 111        { 0xa92c, 0x00000000 },
 112        { 0xa930, 0x00020000 },
 113        { 0xa934, 0x02070106 },
 114        { 0xa938, 0x00010100 },
 115        { 0xa93c, 0x00401c00 },
 116        { 0xa940, 0x00000000 },
 117        { 0xa944, 0x00000000 },
 118        { 0xa948, 0x10000e00 },
 119        { 0xa94c, 0x02000004 },
 120        { 0xa950, 0x00000001 },
 121        { 0xa954, 0x00000004 },
 122        { 0xa960, 0x00060000 },
 123        { 0xaa3c, 0x00001c00 },
 124        { 0xaa54, 0x00000004 },
 125        { 0xaa60, 0x00060000 },
 126        { 0 }
 127};
 128
 129static const struct gt_powermeter ivb_pm_gt2[] = {
 130        { 0xa800, 0x10000000 },
 131        { 0xa804, 0x00033800 },
 132        { 0xa808, 0x00000902 },
 133        { 0xa80c, 0x0c002f00 },
 134        { 0xa810, 0x12000400 },
 135        { 0xa814, 0x00000000 },
 136        { 0xa818, 0x00d20800 },
 137        { 0xa81c, 0x00000002 },
 138        { 0xa820, 0x03004b02 },
 139        { 0xa824, 0x00000600 },
 140        { 0xa828, 0x07000773 },
 141        { 0xa82c, 0x00000000 },
 142        { 0xa830, 0x00010032 },
 143        { 0xa834, 0x1520040d },
 144        { 0xa838, 0x00020105 },
 145        { 0xa83c, 0x00083700 },
 146        { 0xa840, 0x0000151d },
 147        { 0xa844, 0x00000000 },
 148        { 0xa848, 0x20001b00 },
 149        { 0xa84c, 0x0a000010 },
 150        { 0xa850, 0x00000000 },
 151        { 0xa854, 0x00000008 },
 152        { 0xa858, 0x00000008 },
 153        { 0xa85c, 0x00000000 },
 154        { 0xa860, 0x00020000 },
 155        { 0xa248, 0x0000221e },
 156        { 0xa900, 0x00000000 },
 157        { 0xa904, 0x00003500 },
 158        { 0xa908, 0x00000000 },
 159        { 0xa90c, 0x0c000000 },
 160        { 0xa910, 0x12000500 },
 161        { 0xa914, 0x00000000 },
 162        { 0xa918, 0x00b20000 },
 163        { 0xa91c, 0x00000000 },
 164        { 0xa920, 0x08004b02 },
 165        { 0xa924, 0x00000200 },
 166        { 0xa928, 0x07000820 },
 167        { 0xa92c, 0x00000000 },
 168        { 0xa930, 0x00030000 },
 169        { 0xa934, 0x050f020d },
 170        { 0xa938, 0x00020300 },
 171        { 0xa93c, 0x00903900 },
 172        { 0xa940, 0x00000000 },
 173        { 0xa944, 0x00000000 },
 174        { 0xa948, 0x20001b00 },
 175        { 0xa94c, 0x0a000010 },
 176        { 0xa950, 0x00000000 },
 177        { 0xa954, 0x00000008 },
 178        { 0xa960, 0x00110000 },
 179        { 0xaa3c, 0x00003900 },
 180        { 0xaa54, 0x00000008 },
 181        { 0xaa60, 0x00110000 },
 182        { 0 }
 183};
 184
 185static const struct gt_powermeter ivb_pm_gt2_17w[] = {
 186        { 0xa800, 0x20000000 },
 187        { 0xa804, 0x000e3800 },
 188        { 0xa808, 0x00000806 },
 189        { 0xa80c, 0x0c002f00 },
 190        { 0xa810, 0x0c000800 },
 191        { 0xa814, 0x00000000 },
 192        { 0xa818, 0x00d20d00 },
 193        { 0xa81c, 0x000000ff },
 194        { 0xa820, 0x03004b02 },
 195        { 0xa824, 0x00000600 },
 196        { 0xa828, 0x07000773 },
 197        { 0xa82c, 0x00000000 },
 198        { 0xa830, 0x00020032 },
 199        { 0xa834, 0x1520040d },
 200        { 0xa838, 0x00020105 },
 201        { 0xa83c, 0x00083700 },
 202        { 0xa840, 0x000016ff },
 203        { 0xa844, 0x00000000 },
 204        { 0xa848, 0xff000000 },
 205        { 0xa84c, 0x0a000010 },
 206        { 0xa850, 0x00000002 },
 207        { 0xa854, 0x00000008 },
 208        { 0xa858, 0x0000000f },
 209        { 0xa85c, 0x00000000 },
 210        { 0xa860, 0x00020000 },
 211        { 0xa248, 0x0000221e },
 212        { 0xa900, 0x00000000 },
 213        { 0xa904, 0x00003800 },
 214        { 0xa908, 0x00000000 },
 215        { 0xa90c, 0x0c000000 },
 216        { 0xa910, 0x12000800 },
 217        { 0xa914, 0x00000000 },
 218        { 0xa918, 0x00b20000 },
 219        { 0xa91c, 0x00000000 },
 220        { 0xa920, 0x08004b02 },
 221        { 0xa924, 0x00000300 },
 222        { 0xa928, 0x01000820 },
 223        { 0xa92c, 0x00000000 },
 224        { 0xa930, 0x00030000 },
 225        { 0xa934, 0x15150406 },
 226        { 0xa938, 0x00020300 },
 227        { 0xa93c, 0x00903900 },
 228        { 0xa940, 0x00000000 },
 229        { 0xa944, 0x00000000 },
 230        { 0xa948, 0x20001b00 },
 231        { 0xa94c, 0x0a000010 },
 232        { 0xa950, 0x00000000 },
 233        { 0xa954, 0x00000008 },
 234        { 0xa960, 0x00110000 },
 235        { 0xaa3c, 0x00003900 },
 236        { 0xaa54, 0x00000008 },
 237        { 0xaa60, 0x00110000 },
 238        { 0 }
 239};
 240
 241static const struct gt_powermeter ivb_pm_gt2_35w[] = {
 242        { 0xa800, 0x00000000 },
 243        { 0xa804, 0x00030400 },
 244        { 0xa808, 0x00000806 },
 245        { 0xa80c, 0x0c002f00 },
 246        { 0xa810, 0x0c000300 },
 247        { 0xa814, 0x00000000 },
 248        { 0xa818, 0x00d20d00 },
 249        { 0xa81c, 0x000000ff },
 250        { 0xa820, 0x03004b02 },
 251        { 0xa824, 0x00000600 },
 252        { 0xa828, 0x07000773 },
 253        { 0xa82c, 0x00000000 },
 254        { 0xa830, 0x00020032 },
 255        { 0xa834, 0x1520040d },
 256        { 0xa838, 0x00020105 },
 257        { 0xa83c, 0x00083700 },
 258        { 0xa840, 0x000016ff },
 259        { 0xa844, 0x00000000 },
 260        { 0xa848, 0xff000000 },
 261        { 0xa84c, 0x0a000010 },
 262        { 0xa850, 0x00000001 },
 263        { 0xa854, 0x00000008 },
 264        { 0xa858, 0x00000008 },
 265        { 0xa85c, 0x00000000 },
 266        { 0xa860, 0x00020000 },
 267        { 0xa248, 0x0000221e },
 268        { 0xa900, 0x00000000 },
 269        { 0xa904, 0x00003800 },
 270        { 0xa908, 0x00000000 },
 271        { 0xa90c, 0x0c000000 },
 272        { 0xa910, 0x12000800 },
 273        { 0xa914, 0x00000000 },
 274        { 0xa918, 0x00b20000 },
 275        { 0xa91c, 0x00000000 },
 276        { 0xa920, 0x08004b02 },
 277        { 0xa924, 0x00000300 },
 278        { 0xa928, 0x01000820 },
 279        { 0xa92c, 0x00000000 },
 280        { 0xa930, 0x00030000 },
 281        { 0xa934, 0x15150406 },
 282        { 0xa938, 0x00020300 },
 283        { 0xa93c, 0x00903900 },
 284        { 0xa940, 0x00000000 },
 285        { 0xa944, 0x00000000 },
 286        { 0xa948, 0x20001b00 },
 287        { 0xa94c, 0x0a000010 },
 288        { 0xa950, 0x00000000 },
 289        { 0xa954, 0x00000008 },
 290        { 0xa960, 0x00110000 },
 291        { 0xaa3c, 0x00003900 },
 292        { 0xaa54, 0x00000008 },
 293        { 0xaa60, 0x00110000 },
 294        { 0 }
 295};
 296
 297/*
 298 * Some vga option roms are used for several chipsets but they only have one
 299 * PCI ID in their header. If we encounter such an option rom, we need to do
 300 * the mapping ourselves.
 301 */
 302
 303u32 map_oprom_vendev(u32 vendev)
 304{
 305        u32 new_vendev = vendev;
 306
 307        switch (vendev) {
 308        case 0x80860102:                /* GT1 Desktop */
 309        case 0x8086010a:                /* GT1 Server */
 310        case 0x80860112:                /* GT2 Desktop */
 311        case 0x80860116:                /* GT2 Mobile */
 312        case 0x80860122:                /* GT2 Desktop >=1.3GHz */
 313        case 0x80860126:                /* GT2 Mobile >=1.3GHz */
 314        case 0x80860156:                /* IVB */
 315        case 0x80860166:                /* IVB */
 316                /* Set to GT1 Mobile */
 317                new_vendev = 0x80860106;
 318                break;
 319        }
 320
 321        return new_vendev;
 322}
 323
 324static inline u32 gtt_read(void *bar, u32 reg)
 325{
 326        return readl(bar + reg);
 327}
 328
 329static inline void gtt_write(void *bar, u32 reg, u32 data)
 330{
 331        writel(data, bar + reg);
 332}
 333
 334static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
 335{
 336        for (; pm && pm->reg; pm++)
 337                gtt_write(bar, pm->reg, pm->value);
 338}
 339
 340#define GTT_RETRY 1000
 341static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
 342{
 343        unsigned try = GTT_RETRY;
 344        u32 data;
 345
 346        while (try--) {
 347                data = gtt_read(bar, reg);
 348                if ((data & mask) == value)
 349                        return 1;
 350                udelay(10);
 351        }
 352
 353        printf("GT init timeout\n");
 354        return 0;
 355}
 356
 357static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
 358{
 359        u32 reg32;
 360
 361        debug("GT Power Management Init, silicon = %#x\n", rev);
 362
 363        if (rev < IVB_STEP_C0) {
 364                /* 1: Enable force wake */
 365                gtt_write(gtt_bar, 0xa18c, 0x00000001);
 366                gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
 367        } else {
 368                gtt_write(gtt_bar, 0xa180, 1 << 5);
 369                gtt_write(gtt_bar, 0xa188, 0xffff0001);
 370                gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
 371        }
 372
 373        if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
 374                /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
 375                reg32 = gtt_read(gtt_bar, 0x42004);
 376                reg32 |= (1 << 14) | (1 << 15);
 377                gtt_write(gtt_bar, 0x42004, reg32);
 378        }
 379
 380        if (rev >= IVB_STEP_A0) {
 381                /* Display Reset Acknowledge Settings */
 382                reg32 = gtt_read(gtt_bar, 0x45010);
 383                reg32 |= (1 << 1) | (1 << 0);
 384                gtt_write(gtt_bar, 0x45010, reg32);
 385        }
 386
 387        /* 2: Get GT SKU from GTT+0x911c[13] */
 388        reg32 = gtt_read(gtt_bar, 0x911c);
 389        if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
 390                if (reg32 & (1 << 13)) {
 391                        debug("SNB GT1 Power Meter Weights\n");
 392                        gtt_write_powermeter(gtt_bar, snb_pm_gt1);
 393                } else {
 394                        debug("SNB GT2 Power Meter Weights\n");
 395                        gtt_write_powermeter(gtt_bar, snb_pm_gt2);
 396                }
 397        } else {
 398                u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
 399
 400                if (reg32 & (1 << 13)) {
 401                        /* GT1 SKU */
 402                        debug("IVB GT1 Power Meter Weights\n");
 403                        gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
 404                } else {
 405                        /* GT2 SKU */
 406                        u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
 407                        tdp /= (1 << unit);
 408
 409                        if (tdp <= 17) {
 410                                /* <=17W ULV */
 411                                debug("IVB GT2 17W Power Meter Weights\n");
 412                                gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
 413                        } else if ((tdp >= 25) && (tdp <= 35)) {
 414                                /* 25W-35W */
 415                                debug("IVB GT2 25W-35W Power Meter Weights\n");
 416                                gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
 417                        } else {
 418                                /* All others */
 419                                debug("IVB GT2 35W Power Meter Weights\n");
 420                                gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
 421                        }
 422                }
 423        }
 424
 425        /* 3: Gear ratio map */
 426        gtt_write(gtt_bar, 0xa004, 0x00000010);
 427
 428        /* 4: GFXPAUSE */
 429        gtt_write(gtt_bar, 0xa000, 0x00070020);
 430
 431        /* 5: Dynamic EU trip control */
 432        gtt_write(gtt_bar, 0xa080, 0x00000004);
 433
 434        /* 6: ECO bits */
 435        reg32 = gtt_read(gtt_bar, 0xa180);
 436        reg32 |= (1 << 26) | (1 << 31);
 437        /* (bit 20=1 for SNB step D1+ / IVB A0+) */
 438        if (rev >= SNB_STEP_D1)
 439                reg32 |= (1 << 20);
 440        gtt_write(gtt_bar, 0xa180, reg32);
 441
 442        /* 6a: for SnB step D2+ only */
 443        if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
 444            (rev >= SNB_STEP_D2)) {
 445                reg32 = gtt_read(gtt_bar, 0x9400);
 446                reg32 |= (1 << 7);
 447                gtt_write(gtt_bar, 0x9400, reg32);
 448
 449                reg32 = gtt_read(gtt_bar, 0x941c);
 450                reg32 &= 0xf;
 451                reg32 |= (1 << 1);
 452                gtt_write(gtt_bar, 0x941c, reg32);
 453                gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
 454        }
 455
 456        if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
 457                reg32 = gtt_read(gtt_bar, 0x907c);
 458                reg32 |= (1 << 16);
 459                gtt_write(gtt_bar, 0x907c, reg32);
 460
 461                /* 6b: Clocking reset controls */
 462                gtt_write(gtt_bar, 0x9424, 0x00000001);
 463        } else {
 464                /* 6b: Clocking reset controls */
 465                gtt_write(gtt_bar, 0x9424, 0x00000000);
 466        }
 467
 468        /* 7 */
 469        if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
 470                gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
 471                /* Mailbox Cmd for RC6 VID */
 472                gtt_write(gtt_bar, 0x138124, 0x80000004);
 473                if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
 474                        gtt_write(gtt_bar, 0x138124, 0x8000000a);
 475                gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
 476        }
 477
 478        /* 8 */
 479        gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
 480        gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
 481        gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
 482        gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
 483        gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
 484        gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
 485
 486        /* 9 */
 487        gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
 488        gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
 489        gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
 490
 491        /* 10 */
 492        gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
 493        gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
 494        gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
 495        gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
 496        gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
 497
 498        /* 11 */
 499        gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
 500        gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
 501        gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
 502        gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
 503        gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
 504        gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
 505        gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
 506
 507        /* 11a: Enable Render Standby (RC6) */
 508        if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
 509                /*
 510                 * IvyBridge should also support DeepRenderStandby.
 511                 *
 512                 * Unfortunately it does not work reliably on all SKUs so
 513                 * disable it here and it can be enabled by the kernel.
 514                 */
 515                gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
 516        } else {
 517                gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
 518        }
 519
 520        /* 12: Normal Frequency Request */
 521        /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
 522        reg32 = readl(MCHBAR_REG(0x5998));
 523        reg32 >>= 16;
 524        reg32 &= 0xef;
 525        reg32 <<= 25;
 526        gtt_write(gtt_bar, 0xa008, reg32);
 527
 528        /* 13: RP Control */
 529        gtt_write(gtt_bar, 0xa024, 0x00000592);
 530
 531        /* 14: Enable PM Interrupts */
 532        gtt_write(gtt_bar, 0x4402c, 0x03000076);
 533
 534        /* Clear 0x6c024 [8:6] */
 535        reg32 = gtt_read(gtt_bar, 0x6c024);
 536        reg32 &= ~0x000001c0;
 537        gtt_write(gtt_bar, 0x6c024, reg32);
 538
 539        return 0;
 540}
 541
 542int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
 543{
 544        const void *blob = gd->fdt_blob;
 545        int node = dev->of_offset;
 546        u32 reg32, cycle_delay;
 547
 548        debug("GT Power Management Init (post VBIOS)\n");
 549
 550        /* 15: Deassert Force Wake */
 551        if (rev < IVB_STEP_C0) {
 552                gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
 553                gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
 554        } else {
 555                gtt_write(gtt_bar, 0xa188, 0x1fffe);
 556                if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
 557                        gtt_write(gtt_bar, 0xa188,
 558                                  gtt_read(gtt_bar, 0xa188) | 1);
 559                }
 560        }
 561
 562        /* 16: SW RC Control */
 563        gtt_write(gtt_bar, 0xa094, 0x00060000);
 564
 565        /* Setup Digital Port Hotplug */
 566        reg32 = gtt_read(gtt_bar, 0xc4030);
 567        if (!reg32) {
 568                u32 dp_hotplug[3];
 569
 570                if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
 571                                         dp_hotplug, ARRAY_SIZE(dp_hotplug)))
 572                        return -EINVAL;
 573
 574                reg32 = (dp_hotplug[0] & 0x7) << 2;
 575                reg32 |= (dp_hotplug[0] & 0x7) << 10;
 576                reg32 |= (dp_hotplug[0] & 0x7) << 18;
 577                gtt_write(gtt_bar, 0xc4030, reg32);
 578        }
 579
 580        /* Setup Panel Power On Delays */
 581        reg32 = gtt_read(gtt_bar, 0xc7208);
 582        if (!reg32) {
 583                reg32 = (unsigned)fdtdec_get_int(blob, node,
 584                                                 "panel-port-select", 0) << 30;
 585                reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
 586                                << 16;
 587                reg32 |= fdtdec_get_int(blob, node,
 588                                        "panel-power-backlight-on-delay", 0);
 589                gtt_write(gtt_bar, 0xc7208, reg32);
 590        }
 591
 592        /* Setup Panel Power Off Delays */
 593        reg32 = gtt_read(gtt_bar, 0xc720c);
 594        if (!reg32) {
 595                reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
 596                                << 16;
 597                reg32 |= fdtdec_get_int(blob, node,
 598                                        "panel-power-backlight-off-delay", 0);
 599                gtt_write(gtt_bar, 0xc720c, reg32);
 600        }
 601
 602        /* Setup Panel Power Cycle Delay */
 603        cycle_delay = fdtdec_get_int(blob, node,
 604                                     "intel,panel-power-cycle-delay", 0);
 605        if (cycle_delay) {
 606                reg32 = gtt_read(gtt_bar, 0xc7210);
 607                reg32 &= ~0xff;
 608                reg32 |= cycle_delay;
 609                gtt_write(gtt_bar, 0xc7210, reg32);
 610        }
 611
 612        /* Enable Backlight if needed */
 613        reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
 614        if (reg32) {
 615                gtt_write(gtt_bar, 0x48250, (1 << 31));
 616                gtt_write(gtt_bar, 0x48254, reg32);
 617        }
 618        reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
 619        if (reg32) {
 620                gtt_write(gtt_bar, 0xc8250, (1 << 31));
 621                gtt_write(gtt_bar, 0xc8254, reg32);
 622        }
 623
 624        return 0;
 625}
 626
 627/*
 628 * Some vga option roms are used for several chipsets but they only have one
 629 * PCI ID in their header. If we encounter such an option rom, we need to do
 630 * the mapping ourselves.
 631 */
 632
 633uint32_t board_map_oprom_vendev(uint32_t vendev)
 634{
 635        switch (vendev) {
 636        case 0x80860102:                /* GT1 Desktop */
 637        case 0x8086010a:                /* GT1 Server */
 638        case 0x80860112:                /* GT2 Desktop */
 639        case 0x80860116:                /* GT2 Mobile */
 640        case 0x80860122:                /* GT2 Desktop >=1.3GHz */
 641        case 0x80860126:                /* GT2 Mobile >=1.3GHz */
 642        case 0x80860156:                /* IVB */
 643        case 0x80860166:                /* IVB */
 644                return 0x80860106;      /* GT1 Mobile */
 645        }
 646
 647        return vendev;
 648}
 649
 650static int int15_handler(void)
 651{
 652        int res = 0;
 653
 654        debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
 655
 656        switch (M.x86.R_AX) {
 657        case 0x5f34:
 658                /*
 659                 * Set Panel Fitting Hook:
 660                 *  bit 2 = Graphics Stretching
 661                 *  bit 1 = Text Stretching
 662                 *  bit 0 = Centering (do not set with bit1 or bit2)
 663                 *  0     = video bios default
 664                 */
 665                M.x86.R_AX = 0x005f;
 666                M.x86.R_CL = 0x00; /* Use video bios default */
 667                res = 1;
 668                break;
 669        case 0x5f35:
 670                /*
 671                 * Boot Display Device Hook:
 672                 *  bit 0 = CRT
 673                 *  bit 1 = TV (eDP)
 674                 *  bit 2 = EFP
 675                 *  bit 3 = LFP
 676                 *  bit 4 = CRT2
 677                 *  bit 5 = TV2 (eDP)
 678                 *  bit 6 = EFP2
 679                 *  bit 7 = LFP2
 680                 */
 681                M.x86.R_AX = 0x005f;
 682                M.x86.R_CX = 0x0000; /* Use video bios default */
 683                res = 1;
 684                break;
 685        case 0x5f51:
 686                /*
 687                 * Hook to select active LFP configuration:
 688                 *  00h = No LVDS, VBIOS does not enable LVDS
 689                 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
 690                 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
 691                 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
 692                 */
 693                M.x86.R_AX = 0x005f;
 694                M.x86.R_CX = 0x0003; /* eDP */
 695                res = 1;
 696                break;
 697        case 0x5f70:
 698                switch (M.x86.R_CH) {
 699                case 0:
 700                        /* Get Mux */
 701                        M.x86.R_AX = 0x005f;
 702                        M.x86.R_CX = 0x0000;
 703                        res = 1;
 704                        break;
 705                case 1:
 706                        /* Set Mux */
 707                        M.x86.R_AX = 0x005f;
 708                        M.x86.R_CX = 0x0000;
 709                        res = 1;
 710                        break;
 711                case 2:
 712                        /* Get SG/Non-SG mode */
 713                        M.x86.R_AX = 0x005f;
 714                        M.x86.R_CX = 0x0000;
 715                        res = 1;
 716                        break;
 717                default:
 718                        /* Interrupt was not handled */
 719                        debug("Unknown INT15 5f70 function: 0x%02x\n",
 720                              M.x86.R_CH);
 721                        break;
 722                }
 723                break;
 724        case 0x5fac:
 725                res = 1;
 726                break;
 727        default:
 728                debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
 729                break;
 730        }
 731        return res;
 732}
 733
 734void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
 735{
 736        u32 reg32;
 737        u16 reg16;
 738        u8 reg8;
 739
 740        dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
 741        switch (reg16) {
 742        case 0x0102: /* GT1 Desktop */
 743        case 0x0106: /* GT1 Mobile */
 744        case 0x010a: /* GT1 Server */
 745        case 0x0112: /* GT2 Desktop */
 746        case 0x0116: /* GT2 Mobile */
 747        case 0x0122: /* GT2 Desktop >=1.3GHz */
 748        case 0x0126: /* GT2 Mobile >=1.3GHz */
 749        case 0x0156: /* IvyBridge */
 750        case 0x0166: /* IvyBridge */
 751                break;
 752        default:
 753                debug("Graphics not supported by this CPU/chipset\n");
 754                return;
 755        }
 756
 757        debug("Initialising Graphics\n");
 758
 759        /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
 760        dm_pci_read_config16(dev, GGC, &reg16);
 761        reg16 &= ~0x00f8;
 762        reg16 |= 1 << 3;
 763        /* Program GTT memory by setting GGC[9:8] = 2MB */
 764        reg16 &= ~0x0300;
 765        reg16 |= 2 << 8;
 766        /* Enable VGA decode */
 767        reg16 &= ~0x0002;
 768        dm_pci_write_config16(dev, GGC, reg16);
 769
 770        /* Enable 256MB aperture */
 771        dm_pci_read_config8(video_dev, MSAC, &reg8);
 772        reg8 &= ~0x06;
 773        reg8 |= 0x02;
 774        dm_pci_write_config8(video_dev, MSAC, reg8);
 775
 776        /* Erratum workarounds */
 777        reg32 = readl(MCHBAR_REG(0x5f00));
 778        reg32 |= (1 << 9) | (1 << 10);
 779        writel(reg32, MCHBAR_REG(0x5f00));
 780
 781        /* Enable SA Clock Gating */
 782        reg32 = readl(MCHBAR_REG(0x5f00));
 783        writel(reg32 | 1, MCHBAR_REG(0x5f00));
 784
 785        /* GPU RC6 workaround for sighting 366252 */
 786        reg32 = readl(MCHBAR_REG(0x5d14));
 787        reg32 |= (1 << 31);
 788        writel(reg32, MCHBAR_REG(0x5d14));
 789
 790        /* VLW */
 791        reg32 = readl(MCHBAR_REG(0x6120));
 792        reg32 &= ~(1 << 0);
 793        writel(reg32, MCHBAR_REG(0x6120));
 794
 795        reg32 = readl(MCHBAR_REG(0x5418));
 796        reg32 |= (1 << 4) | (1 << 5);
 797        writel(reg32, MCHBAR_REG(0x5418));
 798}
 799
 800int gma_func0_init(struct udevice *dev)
 801{
 802#ifdef CONFIG_VIDEO
 803        ulong start;
 804#endif
 805        struct udevice *nbridge;
 806        void *gtt_bar;
 807        ulong base;
 808        u32 reg32;
 809        int ret;
 810        int rev;
 811
 812        /* Enable PCH Display Port */
 813        writew(0x0010, RCB_REG(DISPBDF));
 814        setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 815
 816        ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
 817        if (ret)
 818                return ret;
 819        rev = bridge_silicon_revision(nbridge);
 820        sandybridge_setup_graphics(nbridge, dev);
 821
 822        /* IGD needs to be Bus Master */
 823        dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
 824        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 825        dm_pci_write_config32(dev, PCI_COMMAND, reg32);
 826
 827        /* Use write-combining for the graphics memory, 256MB */
 828        base = dm_pci_read_bar32(dev, 2);
 829        mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
 830        mtrr_commit(true);
 831
 832        gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
 833        debug("GT bar %p\n", gtt_bar);
 834        ret = gma_pm_init_pre_vbios(gtt_bar, rev);
 835        if (ret)
 836                return ret;
 837
 838#ifdef CONFIG_VIDEO
 839        start = get_timer(0);
 840        ret = dm_pci_run_vga_bios(dev, int15_handler,
 841                                  PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
 842        debug("BIOS ran in %lums\n", get_timer(start));
 843#endif
 844        /* Post VBIOS init */
 845        ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
 846        if (ret)
 847                return ret;
 848
 849        return 0;
 850}
 851