LXR uboot/board/atmel/at91sam9263ek/at91sam9263ek.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian@popies.net>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <linux/sizes.h>
  11#include <asm/arch/at91sam9263.h>
  12#include <asm/arch/at91sam9_smc.h>
  13#include <asm/arch/at91_common.h>
  14#include <asm/arch/at91_matrix.h>
  15#include <asm/arch/at91_pio.h>
  16#include <asm/arch/clk.h>
  17#include <asm/io.h>
  18#include <asm/arch/gpio.h>
  19#include <asm/arch/hardware.h>
  20#include <lcd.h>
  21#include <atmel_lcdc.h>
  22#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  23#include <net.h>
  24#endif
  25#include <netdev.h>
  26#include <atmel_mci.h>
  27
  28DECLARE_GLOBAL_DATA_PTR;
  29
  30/* ------------------------------------------------------------------------- */
  31/*
  32 * Miscelaneous platform dependent initialisations
  33 */
  34
  35#ifdef CONFIG_CMD_NAND
  36static void at91sam9263ek_nand_hw_init(void)
  37{
  38        unsigned long csa;
  39        at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  40        at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  41
  42        /* Enable CS3 */
  43        csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  44        writel(csa, &matrix->csa[0]);
  45
  46        /* Enable CS3 */
  47
  48        /* Configure SMC CS3 for NAND/SmartMedia */
  49        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  50                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  51                &smc->cs[3].setup);
  52
  53        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  54                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  55                &smc->cs[3].pulse);
  56
  57        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  58                &smc->cs[3].cycle);
  59        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                AT91_SMC_MODE_EXNW_DISABLE |
  61#ifdef CONFIG_SYS_NAND_DBW_16
  62                       AT91_SMC_MODE_DBW_16 |
  63#else /* CONFIG_SYS_NAND_DBW_8 */
  64                       AT91_SMC_MODE_DBW_8 |
  65#endif
  66                       AT91_SMC_MODE_TDF_CYCLE(2),
  67                &smc->cs[3].mode);
  68
  69        at91_periph_clk_enable(ATMEL_ID_PIOA);
  70        at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  71
  72        /* Configure RDY/BSY */
  73        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  74
  75        /* Enable NandFlash */
  76        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  77}
  78#endif
  79
  80#ifdef CONFIG_MACB
  81static void at91sam9263ek_macb_hw_init(void)
  82{
  83        at91_pio_t      *pio    = (at91_pio_t *) ATMEL_BASE_PIO;
  84
  85        at91_periph_clk_enable(ATMEL_ID_EMAC);
  86
  87        /*
  88         * Disable pull-up on:
  89         *      RXDV (PC25) => PHY normal mode (not Test mode)
  90         *      ERX0 (PE25) => PHY ADDR0
  91         *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  92         *
  93         * PHY has internal pull-down
  94         */
  95        writel(1 << 25, &pio->pioc.pudr);
  96        writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
  97
  98        at91_phy_reset();
  99
 100        /* Re-enable pull-up */
 101        writel(1 << 25, &pio->pioc.puer);
 102        writel((1 << 25) | (1 <<26), &pio->pioe.puer);
 103
 104        at91_macb_hw_init();
 105}
 106#endif
 107
 108#ifdef CONFIG_LCD
 109vidinfo_t panel_info = {
 110        .vl_col =               240,
 111        .vl_row =               320,
 112        .vl_clk =               4965000,
 113        .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
 114                                ATMEL_LCDC_INVFRAME_INVERTED,
 115        .vl_bpix =              3,
 116        .vl_tft =               1,
 117        .vl_hsync_len =         5,
 118        .vl_left_margin =       1,
 119        .vl_right_margin =      33,
 120        .vl_vsync_len =         1,
 121        .vl_upper_margin =      1,
 122        .vl_lower_margin =      0,
 123        .mmio =                 ATMEL_BASE_LCDC,
 124};
 125
 126void lcd_enable(void)
 127{
 128        at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 129}
 130
 131void lcd_disable(void)
 132{
 133        at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 134}
 135
 136static void at91sam9263ek_lcd_hw_init(void)
 137{
 138        at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 139        at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 140        at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 141        at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 142        at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 143        at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 144        at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 145        at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 146        at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 147        at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 148        at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 149        at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 150        at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 151        at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 152        at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 153        at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 154        at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 155        at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 156        at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 157        at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 158        at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 159        at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 160
 161        at91_periph_clk_enable(ATMEL_ID_LCDC);
 162        gd->fb_base = ATMEL_BASE_SRAM0;
 163}
 164
 165#ifdef CONFIG_LCD_INFO
 166#include <nand.h>
 167#include <version.h>
 168
 169#ifndef CONFIG_SYS_NO_FLASH
 170extern flash_info_t flash_info[];
 171#endif
 172
 173void lcd_show_board_info(void)
 174{
 175        ulong dram_size, nand_size;
 176#ifndef CONFIG_SYS_NO_FLASH
 177        ulong flash_size;
 178#endif
 179        int i;
 180        char temp[32];
 181
 182        lcd_printf ("%s\n", U_BOOT_VERSION);
 183        lcd_printf ("(C) 2008 ATMEL Corp\n");
 184        lcd_printf ("at91support@atmel.com\n");
 185        lcd_printf ("%s CPU at %s MHz\n",
 186                ATMEL_CPU_NAME,
 187                strmhz(temp, get_cpu_clk_rate()));
 188
 189        dram_size = 0;
 190        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 191                dram_size += gd->bd->bi_dram[i].size;
 192        nand_size = 0;
 193        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 194                nand_size += nand_info[i].size;
 195#ifndef CONFIG_SYS_NO_FLASH
 196        flash_size = 0;
 197        for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 198                flash_size += flash_info[i].size;
 199#endif
 200        lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 201                dram_size >> 20,
 202                nand_size >> 20 );
 203#ifndef CONFIG_SYS_NO_FLASH
 204        lcd_printf (",\n  %ld MB NOR",
 205                flash_size >> 20);
 206#endif
 207        lcd_puts ("\n");
 208}
 209#endif /* CONFIG_LCD_INFO */
 210#endif
 211
 212#ifdef CONFIG_GENERIC_ATMEL_MCI
 213int board_mmc_init(bd_t *bd)
 214{
 215        at91_mci_hw_init();
 216
 217        return atmel_mci_init((void *)ATMEL_BASE_MCI1);
 218}
 219#endif
 220
 221int board_early_init_f(void)
 222{
 223        at91_periph_clk_enable(ATMEL_ID_PIOA);
 224        at91_periph_clk_enable(ATMEL_ID_PIOB);
 225        at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 226
 227        at91_seriald_hw_init();
 228        return 0;
 229}
 230
 231int board_init(void)
 232{
 233        /* arch number of AT91SAM9263EK-Board */
 234        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 235        /* adress of boot parameters */
 236        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 237
 238#ifdef CONFIG_CMD_NAND
 239        at91sam9263ek_nand_hw_init();
 240#endif
 241#ifdef CONFIG_HAS_DATAFLASH
 242        at91_set_pio_output(AT91_PIO_PORTE, 20, 1);     /* select spi0 clock */
 243        at91_spi0_hw_init(1 << 0);
 244#endif
 245#ifdef CONFIG_MACB
 246        at91sam9263ek_macb_hw_init();
 247#endif
 248#ifdef CONFIG_USB_OHCI_NEW
 249        at91_uhp_hw_init();
 250#endif
 251#ifdef CONFIG_LCD
 252        at91sam9263ek_lcd_hw_init();
 253#endif
 254        return 0;
 255}
 256
 257int dram_init(void)
 258{
 259        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 260                CONFIG_SYS_SDRAM_SIZE);
 261
 262        return 0;
 263}
 264
 265#ifdef CONFIG_RESET_PHY_R
 266void reset_phy(void)
 267{
 268}
 269#endif
 270
 271int board_eth_init(bd_t *bis)
 272{
 273        int rc = 0;
 274#ifdef CONFIG_MACB
 275        rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
 276#endif
 277        return rc;
 278}
 279