1
2
3
4
5
6
7
8
9
10#include <common.h>
11#include <i2c.h>
12#include <asm/io.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/mx6-ddr.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/imx-common/boot_mode.h>
18#include <asm/imx-common/iomux-v3.h>
19#include <asm/imx-common/mxc_i2c.h>
20#include <spl.h>
21
22#include "platinum.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#undef RTT_NOM_120OHM
27
28
29struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
30
31 .dram_sdclk_0 = 0x00020030,
32 .dram_sdclk_1 = 0x00020030,
33 .dram_cas = 0x00020030,
34 .dram_ras = 0x00020030,
35 .dram_reset = 0x00020030,
36
37 .dram_sdcke0 = 0x00003000,
38 .dram_sdcke1 = 0x00003000,
39
40 .dram_sdba2 = 0x00000000,
41
42 .dram_sdodt0 = 0x00003030,
43 .dram_sdodt1 = 0x00003030,
44
45 .dram_sdqs0 = 0x00000030,
46 .dram_sdqs1 = 0x00000030,
47 .dram_sdqs2 = 0x00000030,
48 .dram_sdqs3 = 0x00000030,
49 .dram_sdqs4 = 0x00000030,
50 .dram_sdqs5 = 0x00000030,
51 .dram_sdqs6 = 0x00000030,
52 .dram_sdqs7 = 0x00000030,
53
54 .dram_dqm0 = 0x00020030,
55 .dram_dqm1 = 0x00020030,
56 .dram_dqm2 = 0x00020030,
57 .dram_dqm3 = 0x00020030,
58 .dram_dqm4 = 0x00020030,
59 .dram_dqm5 = 0x00020030,
60 .dram_dqm6 = 0x00020030,
61 .dram_dqm7 = 0x00020030,
62};
63
64
65struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
66
67 .grp_ddr_type = 0x000c0000,
68 .grp_ddrmode_ctl = 0x00020000,
69
70 .grp_ddrpke = 0x00000000,
71
72 .grp_addds = 0x00000030,
73
74 .grp_ctlds = 0x00000030,
75
76 .grp_ddrmode = 0x00020000,
77 .grp_b0ds = 0x00000030,
78 .grp_b1ds = 0x00000030,
79 .grp_b2ds = 0x00000030,
80 .grp_b3ds = 0x00000030,
81 .grp_b4ds = 0x00000030,
82 .grp_b5ds = 0x00000030,
83 .grp_b6ds = 0x00000030,
84 .grp_b7ds = 0x00000030,
85};
86
87
88static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
89 .mem_speed = 1600,
90 .density = 4,
91 .width = 16,
92 .banks = 8,
93 .rowaddr = 15,
94 .coladdr = 10,
95 .pagesz = 2,
96 .trcd = 1375,
97 .trcmin = 4875,
98 .trasmin = 3500,
99};
100
101
102
103
104static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
105
106 .p0_mpwldectrl0 = 0x0044004E,
107 .p0_mpwldectrl1 = 0x001F0023,
108
109 .p0_mpdgctrl0 = 0x02480248,
110 .p0_mpdgctrl1 = 0x0210021C,
111
112 .p0_mprddlctl = 0x42444444,
113
114 .p0_mpwrdlctl = 0x36322C32,
115};
116
117static void spl_dram_init(int width)
118{
119 struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
120 struct mx6_ddr_sysinfo sysinfo = {
121
122 .dsize = width / 32,
123
124 .cs_density = 32,
125
126 .ncs = 1,
127 .cs1_mirror = 1,
128 .rtt_wr = 1 ,
129#ifdef RTT_NOM_120OHM
130 .rtt_nom = 2 ,
131#else
132 .rtt_nom = 1 ,
133#endif
134 .walat = 0,
135 .ralat = 5,
136 .mif3_mode = 3,
137 .bi_on = 1,
138 .sde_to_rst = 0x10,
139 .rst_to_cke = 0x23,
140 .ddr_type = DDR_TYPE_DDR3,
141 };
142
143 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
144 mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
145}
146
147
148
149
150
151
152void board_init_f(ulong dummy)
153{
154
155 arch_cpu_init();
156
157 ccgr_init();
158 gpr_init();
159
160
161 board_early_init_f();
162
163
164 timer_init();
165
166
167 preloader_console_init();
168
169
170 spl_dram_init(32);
171
172
173 memset(__bss_start, 0, __bss_end - __bss_start);
174
175
176
177
178
179 platinum_setup_enet();
180
181
182 board_init_r(NULL, 0);
183}
184