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51#include <common.h>
52#include <netdev.h>
53#include <asm/fsl_serdes.h>
54#include <fm_eth.h>
55#include <fsl_mdio.h>
56#include <malloc.h>
57#include <fdt_support.h>
58#include <fsl_dtsec.h>
59
60#include "../common/ngpixis.h"
61#include "../common/fman.h"
62
63#ifdef CONFIG_FMAN_ENET
64
65#define BRDCFG1_EMI1_SEL_MASK 0x70
66#define BRDCFG1_EMI1_SEL_SLOT1 0x10
67#define BRDCFG1_EMI1_SEL_SLOT2 0x20
68#define BRDCFG1_EMI1_SEL_SLOT5 0x30
69#define BRDCFG1_EMI1_SEL_SLOT6 0x40
70#define BRDCFG1_EMI1_SEL_SLOT7 0x50
71#define BRDCFG1_EMI1_SEL_SLOT3 0x60
72#define BRDCFG1_EMI1_SEL_RGMII 0x00
73#define BRDCFG1_EMI1_EN 0x08
74#define BRDCFG1_EMI2_SEL_MASK 0x06
75#define BRDCFG1_EMI2_SEL_SLOT1 0x00
76#define BRDCFG1_EMI2_SEL_SLOT2 0x02
77
78#define BRDCFG2_REG_GPIO_SEL 0x20
79
80
81#define PHY_BASE_ADDR 0x00
82#define REGNUM 0x00
83#define PORT_NUM_FM1 0x04
84#define PORT_NUM_FM2 0x02
85
86
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89
90
91
92static struct {
93 u8 mask;
94 u8 val;
95} mdio_mux[NUM_FM_PORTS];
96
97
98
99
100
101
102static u8 lane_to_slot[] = {
103 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
104};
105
106
107
108
109
110
111void super_hydra_mux_mdio(u8 mask, u8 val)
112{
113 clrsetbits_8(&pixis->brdcfg1, mask, val);
114}
115
116struct super_hydra_mdio {
117 u8 mask;
118 u8 val;
119 struct mii_dev *realbus;
120};
121
122static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
123 int regnum)
124{
125 struct super_hydra_mdio *priv = bus->priv;
126
127 super_hydra_mux_mdio(priv->mask, priv->val);
128
129 return priv->realbus->read(priv->realbus, addr, devad, regnum);
130}
131
132static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
133 int regnum, u16 value)
134{
135 struct super_hydra_mdio *priv = bus->priv;
136
137 super_hydra_mux_mdio(priv->mask, priv->val);
138
139 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
140}
141
142static int super_hydra_mdio_reset(struct mii_dev *bus)
143{
144 struct super_hydra_mdio *priv = bus->priv;
145
146 return priv->realbus->reset(priv->realbus);
147}
148
149static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
150{
151 struct mii_dev *bus = miiphy_get_dev_by_name(name);
152 struct super_hydra_mdio *priv = bus->priv;
153
154 priv->mask = mask;
155 priv->val = val;
156}
157
158static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
159{
160 struct super_hydra_mdio *hmdio;
161 struct mii_dev *bus = mdio_alloc();
162
163 if (!bus) {
164 printf("Failed to allocate Hydra MDIO bus\n");
165 return -1;
166 }
167
168 hmdio = malloc(sizeof(*hmdio));
169 if (!hmdio) {
170 printf("Failed to allocate Hydra private data\n");
171 free(bus);
172 return -1;
173 }
174
175 bus->read = super_hydra_mdio_read;
176 bus->write = super_hydra_mdio_write;
177 bus->reset = super_hydra_mdio_reset;
178 strcpy(bus->name, fakebusname);
179
180 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
181
182 if (!hmdio->realbus) {
183 printf("No bus with name %s\n", realbusname);
184 free(bus);
185 free(hmdio);
186 return -1;
187 }
188
189 bus->priv = hmdio;
190
191 return mdio_register(bus);
192}
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213
214void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
215 enum fm_port port, int offset)
216{
217 enum srds_prtcl device;
218 int lane, slot, phy;
219 char alias[32];
220
221
222
223 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
224 device = serdes_device_from_fm_port(port);
225 lane = serdes_get_first_lane(device);
226 slot = lane_to_slot[lane];
227 phy = fm_info_get_phy_address(port);
228
229 sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
230 fdt_set_phy_handle(fdt, compat, addr, alias);
231 }
232}
233
234#define PIXIS_SW2_LANE_23_SEL 0x80
235#define PIXIS_SW2_LANE_45_SEL 0x40
236#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
237#define PIXIS_SW2_LANE_67_SEL_5 0x00
238#define PIXIS_SW2_LANE_67_SEL_6 0x20
239#define PIXIS_SW2_LANE_67_SEL_7 0x10
240#define PIXIS_SW2_LANE_8_SEL 0x08
241#define PIXIS_SW2_LANE_1617_SEL 0x04
242#define PIXIS_SW11_LANE_9_SEL 0x04
243
244
245
246
247
248
249
250
251static void initialize_lane_to_slot(void)
252{
253 u8 sw2 = in_8(&PIXIS_SW(2));
254
255 u8 sw11 = in_8(&PIXIS_SW(9));
256
257 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
258 lane_to_slot[3] = lane_to_slot[2];
259
260 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
261 lane_to_slot[5] = lane_to_slot[4];
262
263 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
264 case PIXIS_SW2_LANE_67_SEL_5:
265 lane_to_slot[6] = 5;
266 break;
267 case PIXIS_SW2_LANE_67_SEL_6:
268 lane_to_slot[6] = 6;
269 break;
270 case PIXIS_SW2_LANE_67_SEL_7:
271 lane_to_slot[6] = 7;
272 break;
273 }
274 lane_to_slot[7] = lane_to_slot[6];
275
276 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
277 lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
278
279 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
280 lane_to_slot[17] = lane_to_slot[16];
281}
282
283#endif
284
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294
295
296void fdt_fixup_board_enet(void *fdt)
297{
298#ifdef CONFIG_FMAN_ENET
299 enum fm_port i;
300 int lane, slot;
301
302 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
303 int idx = i - FM1_DTSEC1;
304
305 switch (fm_info_get_enet_if(i)) {
306 case PHY_INTERFACE_MODE_SGMII:
307 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
308 if (lane >= 0) {
309 char alias[32];
310
311 slot = lane_to_slot[lane];
312 sprintf(alias, "hydra_sg_slot%u", slot);
313 fdt_status_okay_by_alias(fdt, alias);
314 debug("Enabled MDIO node %s (slot %i)\n",
315 alias, slot);
316 }
317 break;
318 case PHY_INTERFACE_MODE_RGMII:
319 fdt_status_okay_by_alias(fdt, "hydra_rg");
320 debug("Enabled MDIO node hydra_rg\n");
321 break;
322 default:
323 break;
324 }
325 }
326
327 lane = serdes_get_first_lane(XAUI_FM1);
328 if (lane >= 0) {
329 char alias[32];
330
331 slot = lane_to_slot[lane];
332 sprintf(alias, "hydra_xg_slot%u", slot);
333 fdt_status_okay_by_alias(fdt, alias);
334 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
335 }
336
337#if CONFIG_SYS_NUM_FMAN == 2
338 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
339 int idx = i - FM2_DTSEC1;
340
341 switch (fm_info_get_enet_if(i)) {
342 case PHY_INTERFACE_MODE_SGMII:
343 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
344 if (lane >= 0) {
345 char alias[32];
346
347 slot = lane_to_slot[lane];
348 sprintf(alias, "hydra_sg_slot%u", slot);
349 fdt_status_okay_by_alias(fdt, alias);
350 debug("Enabled MDIO node %s (slot %i)\n",
351 alias, slot);
352 }
353 break;
354 case PHY_INTERFACE_MODE_RGMII:
355 fdt_status_okay_by_alias(fdt, "hydra_rg");
356 debug("Enabled MDIO node hydra_rg\n");
357 break;
358 default:
359 break;
360 }
361 }
362
363 lane = serdes_get_first_lane(XAUI_FM2);
364 if (lane >= 0) {
365 char alias[32];
366
367 slot = lane_to_slot[lane];
368 sprintf(alias, "hydra_xg_slot%u", slot);
369 fdt_status_okay_by_alias(fdt, alias);
370 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
371 }
372#endif
373#endif
374}
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417int board_eth_init(bd_t *bis)
418{
419#ifdef CONFIG_FMAN_ENET
420 struct fsl_pq_mdio_info dtsec_mdio_info;
421 struct tgec_mdio_info tgec_mdio_info;
422 unsigned int i, slot;
423 int lane;
424 struct mii_dev *bus;
425 int qsgmii;
426 int phy_real_addr;
427 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
428 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
429 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
430
431 printf("Initializing Fman\n");
432
433 initialize_lane_to_slot();
434
435
436 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
437
438 memset(mdio_mux, 0, sizeof(mdio_mux));
439
440 dtsec_mdio_info.regs =
441 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
442 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
443
444
445 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
446
447 tgec_mdio_info.regs =
448 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
449 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
450
451
452 fm_tgec_mdio_init(bis, &tgec_mdio_info);
453
454
455 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
456 "SUPER_HYDRA_RGMII_MDIO");
457 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
458 "SUPER_HYDRA_FM1_SGMII_MDIO");
459 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
460 "SUPER_HYDRA_FM2_SGMII_MDIO");
461 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
462 "SUPER_HYDRA_FM3_SGMII_MDIO");
463 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
464 "SUPER_HYDRA_FM1_TGEC_MDIO");
465 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
466 "SUPER_HYDRA_FM2_TGEC_MDIO");
467
468
469
470
471
472
473 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
474 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
475 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
476
477#if (CONFIG_SYS_NUM_FMAN == 2)
478 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
479 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
480 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
481 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
482 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
483#endif
484
485 switch (srds_prtcl) {
486 case 0:
487 case 3:
488 case 4:
489 case 6:
490 case 0x11:
491 case 0x2a:
492 case 0x34:
493 case 0x36:
494 fm_info_set_phy_address(FM1_DTSEC3,
495 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
496 fm_info_set_phy_address(FM1_DTSEC4,
497 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
498 break;
499 case 1:
500 case 2:
501 case 5:
502 case 7:
503 case 0x35:
504 fm_info_set_phy_address(FM1_DTSEC3,
505 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
506 fm_info_set_phy_address(FM1_DTSEC4,
507 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
508 break;
509 default:
510 printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
511 break;
512 }
513
514 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
515 int idx = i - FM1_DTSEC1;
516
517 switch (fm_info_get_enet_if(i)) {
518 case PHY_INTERFACE_MODE_SGMII:
519 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
520 if (lane < 0)
521 break;
522 slot = lane_to_slot[lane];
523 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
524 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
525 idx + 1, slot);
526 switch (slot) {
527 case 1:
528 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
529 BRDCFG1_EMI1_EN;
530 break;
531 case 2:
532 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
533 BRDCFG1_EMI1_EN;
534 break;
535 case 3:
536 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
537 BRDCFG1_EMI1_EN;
538 break;
539 case 5:
540 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
541 BRDCFG1_EMI1_EN;
542 break;
543 case 6:
544 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
545 BRDCFG1_EMI1_EN;
546 break;
547 case 7:
548 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
549 BRDCFG1_EMI1_EN;
550 break;
551 };
552
553 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
554 mdio_mux[i].mask, mdio_mux[i].val);
555 fm_info_set_mdio(i,
556 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
557 break;
558 case PHY_INTERFACE_MODE_RGMII:
559
560
561
562
563
564
565 debug("FM1@DTSEC%u is RGMII at address %u\n",
566 idx + 1, 0);
567 fm_info_set_phy_address(i, 0);
568 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
569 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
570 BRDCFG1_EMI1_EN;
571 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
572 mdio_mux[i].mask, mdio_mux[i].val);
573 fm_info_set_mdio(i,
574 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
575 break;
576 case PHY_INTERFACE_MODE_NONE:
577 fm_info_set_phy_address(i, 0);
578 break;
579 default:
580 printf("Fman1: DTSEC%u set to unknown interface %i\n",
581 idx + 1, fm_info_get_enet_if(i));
582 fm_info_set_phy_address(i, 0);
583 break;
584 }
585 }
586
587 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
588 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
589
590 if (qsgmii) {
591 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
592 if (fm_info_get_enet_if(i) ==
593 PHY_INTERFACE_MODE_SGMII) {
594 phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
595 fm_info_set_phy_address(i, phy_real_addr);
596 }
597 }
598 switch (srds_prtcl) {
599 case 0x00:
600 case 0x03:
601 case 0x04:
602 case 0x06:
603 case 0x11:
604 case 0x2a:
605 case 0x34:
606 case 0x36:
607 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
608 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
609 break;
610 case 0x01:
611 case 0x02:
612 case 0x05:
613 case 0x07:
614 case 0x35:
615 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
616 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
617 break;
618 default:
619 break;
620 }
621 }
622
623
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631
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633
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635
636 lane = serdes_get_first_lane(XAUI_FM1);
637 if (lane >= 0) {
638 debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
639 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
640 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
641 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
642 mdio_mux[i].mask, mdio_mux[i].val);
643 }
644
645 fm_info_set_mdio(FM1_10GEC1,
646 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
647
648#if (CONFIG_SYS_NUM_FMAN == 2)
649 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
650 int idx = i - FM2_DTSEC1;
651
652 switch (fm_info_get_enet_if(i)) {
653 case PHY_INTERFACE_MODE_SGMII:
654 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
655 if (lane < 0)
656 break;
657 slot = lane_to_slot[lane];
658 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
659 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
660 idx + 1, slot);
661 switch (slot) {
662 case 1:
663 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
664 BRDCFG1_EMI1_EN;
665 break;
666 case 2:
667 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
668 BRDCFG1_EMI1_EN;
669 break;
670 case 3:
671 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
672 BRDCFG1_EMI1_EN;
673 break;
674 case 5:
675 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
676 BRDCFG1_EMI1_EN;
677 break;
678 case 6:
679 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
680 BRDCFG1_EMI1_EN;
681 break;
682 case 7:
683 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
684 BRDCFG1_EMI1_EN;
685 break;
686 };
687
688 if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
689 super_hydra_mdio_set_mux(
690 "SUPER_HYDRA_FM3_SGMII_MDIO",
691 mdio_mux[i].mask,
692 mdio_mux[i].val);
693 fm_info_set_mdio(i, miiphy_get_dev_by_name(
694 "SUPER_HYDRA_FM3_SGMII_MDIO"));
695 } else {
696 super_hydra_mdio_set_mux(
697 "SUPER_HYDRA_FM2_SGMII_MDIO",
698 mdio_mux[i].mask,
699 mdio_mux[i].val);
700 fm_info_set_mdio(i, miiphy_get_dev_by_name(
701 "SUPER_HYDRA_FM2_SGMII_MDIO"));
702 }
703
704 break;
705 case PHY_INTERFACE_MODE_RGMII:
706
707
708
709
710
711
712 debug("FM2@DTSEC%u is RGMII at address %u\n",
713 idx + 1, 1);
714 fm_info_set_phy_address(i, 1);
715 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
716 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
717 BRDCFG1_EMI1_EN;
718 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
719 mdio_mux[i].mask, mdio_mux[i].val);
720 fm_info_set_mdio(i,
721 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
722 break;
723 case PHY_INTERFACE_MODE_NONE:
724 fm_info_set_phy_address(i, 0);
725 break;
726 default:
727 printf("Fman2: DTSEC%u set to unknown interface %i\n",
728 idx + 1, fm_info_get_enet_if(i));
729 fm_info_set_phy_address(i, 0);
730 break;
731 }
732 }
733
734 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
735 set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
736 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
737 set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752 lane = serdes_get_first_lane(XAUI_FM2);
753 if (lane >= 0) {
754 debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
755 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
756 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
757 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
758 mdio_mux[i].mask, mdio_mux[i].val);
759 }
760
761 fm_info_set_mdio(FM2_10GEC1,
762 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
763
764#endif
765
766 cpu_eth_init(bis);
767#endif
768
769 return pci_eth_init(bis);
770}
771