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15#include <common.h>
16#include <command.h>
17#include <pci.h>
18#include <asm/processor.h>
19#include <asm/immap_86xx.h>
20#include <asm/fsl_pci.h>
21#include <fsl_ddr_sdram.h>
22#include <asm/fsl_serdes.h>
23#include <libfdt.h>
24#include <fdt_support.h>
25
26long int fixed_sdram (void);
27
28int board_early_init_f (void)
29{
30 return 0;
31}
32
33int checkboard (void)
34{
35 puts ("Board: Wind River SBC8641D\n");
36
37 return 0;
38}
39
40phys_size_t initdram (int board_type)
41{
42 long dram_size = 0;
43
44#if defined(CONFIG_SPD_EEPROM)
45 dram_size = fsl_ddr_sdram();
46#else
47 dram_size = fixed_sdram ();
48#endif
49
50 debug (" DDR: ");
51 return dram_size;
52}
53
54#if defined(CONFIG_SYS_DRAM_TEST)
55int testdram (void)
56{
57 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
58 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
59 uint *p;
60
61 puts ("SDRAM test phase 1:\n");
62 for (p = pstart; p < pend; p++)
63 *p = 0xaaaaaaaa;
64
65 for (p = pstart; p < pend; p++) {
66 if (*p != 0xaaaaaaaa) {
67 printf ("SDRAM test fails at: %08x\n", (uint) p);
68 return 1;
69 }
70 }
71
72 puts ("SDRAM test phase 2:\n");
73 for (p = pstart; p < pend; p++)
74 *p = 0x55555555;
75
76 for (p = pstart; p < pend; p++) {
77 if (*p != 0x55555555) {
78 printf ("SDRAM test fails at: %08x\n", (uint) p);
79 return 1;
80 }
81 }
82
83 puts ("SDRAM test passed.\n");
84 return 0;
85}
86#endif
87
88#if !defined(CONFIG_SPD_EEPROM)
89
90
91
92long int fixed_sdram (void)
93{
94#if !defined(CONFIG_SYS_RAMBOOT)
95 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
96 volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
97
98 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
99 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
100 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
101 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
102 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
103 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
104 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
105 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
106 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
107 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
108 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
109 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
110 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
111 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
112 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
113 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
114 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
118
119 asm ("sync;isync");
120
121 udelay (500);
122
123 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
124 asm ("sync; isync");
125
126 udelay (500);
127 ddr = &immap->im_ddr2;
128
129 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
130 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
131 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
132 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
133 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
134 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
135 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
136 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
137 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
138 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
139 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
140 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
141 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
142 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
143 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
144 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
145 ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
146 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
147 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
148 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
149
150 asm ("sync;isync");
151
152 udelay (500);
153
154 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
155 asm ("sync; isync");
156
157 udelay (500);
158#endif
159 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
160}
161#endif
162
163#if defined(CONFIG_PCI)
164
165
166
167
168void pci_init_board(void)
169{
170 fsl_pcie_init_board(0);
171}
172#endif
173
174
175#if defined(CONFIG_OF_BOARD_SETUP)
176int ft_board_setup(void *blob, bd_t *bd)
177{
178 ft_cpu_setup(blob, bd);
179
180 FT_FSL_PCI_SETUP;
181
182 return 0;
183}
184#endif
185
186void sbc8641d_reset_board (void)
187{
188 puts ("Resetting board....\n");
189}
190
191
192
193
194
195
196unsigned long get_board_sys_clk (ulong dummy)
197{
198 int i;
199 ulong val = 0;
200
201 i = 5;
202 i &= 0x07;
203
204 switch (i) {
205 case 0:
206 val = 33000000;
207 break;
208 case 1:
209 val = 40000000;
210 break;
211 case 2:
212 val = 50000000;
213 break;
214 case 3:
215 val = 66000000;
216 break;
217 case 4:
218 val = 83000000;
219 break;
220 case 5:
221 val = 100000000;
222 break;
223 case 6:
224 val = 134000000;
225 break;
226 case 7:
227 val = 166000000;
228 break;
229 }
230
231 return val;
232}
233
234void board_reset(void)
235{
236#ifdef CONFIG_SYS_RESET_ADDRESS
237 ulong addr = CONFIG_SYS_RESET_ADDRESS;
238
239
240 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
241 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
242 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
243 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
244 __asm__ __volatile__ ("sync");
245 __asm__ __volatile__ ("mtspr 1008, 4");
246 __asm__ __volatile__ ("isync");
247 __asm__ __volatile__ ("sync");
248 __asm__ __volatile__ ("mtspr 1008, 5");
249 __asm__ __volatile__ ("isync");
250 __asm__ __volatile__ ("sync");
251
252
253
254
255
256 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
257 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
258 __asm__ __volatile__ ("mtspr 27, 4");
259 __asm__ __volatile__ ("rfi");
260#endif
261}
262
