LXR uboot/drivers/mmc/hi6220_dw

   1/*
   2 * (C) Copyright 2015 Linaro
   3 * peter.griffin <peter.griffin@linaro.org>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <dwmmc.h>
  10#include <malloc.h>
  11#include <asm-generic/errno.h>
  12
  13#define DWMMC_MAX_CH_NUM                4
  14
  15#define DWMMC_MAX_FREQ                  50000000
  16#define DWMMC_MIN_FREQ                  400000
  17
  18/* Source clock is configured to 100MHz by ATF bl1*/
  19#define MMC0_DEFAULT_FREQ               100000000
  20
  21static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
  22{
  23        host->name = "HiKey DWMMC";
  24
  25        host->dev_index = index;
  26
  27        /* Add the mmc channel to be registered with mmc core */
  28        if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
  29                printf("DWMMC%d registration failed\n", index);
  30                return -1;
  31        }
  32        return 0;
  33}
  34
  35/*
  36 * This function adds the mmc channel to be registered with mmc core.
  37 * index -      mmc channel number.
  38 * regbase -    register base address of mmc channel specified in 'index'.
  39 * bus_width -  operating bus width of mmc channel specified in 'index'.
  40 */
  41int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
  42{
  43        struct dwmci_host *host = NULL;
  44
  45        host = calloc(1, sizeof(struct dwmci_host));
  46        if (!host) {
  47                error("dwmci_host calloc failed!\n");
  48                return -ENOMEM;
  49        }
  50
  51        host->ioaddr = (void *)(ulong)regbase;
  52        host->buswidth = bus_width;
  53        host->bus_hz = MMC0_DEFAULT_FREQ;
  54
  55        return hi6220_dwmci_core_init(host, index);
  56}
  57