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11#include <common.h>
12#include <errno.h>
13#include <malloc.h>
14#include <mmc.h>
15#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/mmc.h>
20#include <asm-generic/gpio.h>
21
22struct sunxi_mmc_host {
23 unsigned mmc_no;
24 uint32_t *mclkreg;
25 unsigned fatal_err;
26 struct sunxi_mmc *reg;
27 struct mmc_config cfg;
28};
29
30
31struct sunxi_mmc_host mmc_host[4];
32
33static int sunxi_mmc_getcd_gpio(int sdc_no)
34{
35 switch (sdc_no) {
36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
40 }
41 return -EINVAL;
42}
43
44static int mmc_resource_init(int sdc_no)
45{
46 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
47 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
48 int cd_pin, ret = 0;
49
50 debug("init mmc %d resource\n", sdc_no);
51
52 switch (sdc_no) {
53 case 0:
54 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
55 mmchost->mclkreg = &ccm->sd0_clk_cfg;
56 break;
57 case 1:
58 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
59 mmchost->mclkreg = &ccm->sd1_clk_cfg;
60 break;
61 case 2:
62 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
63 mmchost->mclkreg = &ccm->sd2_clk_cfg;
64 break;
65 case 3:
66 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
67 mmchost->mclkreg = &ccm->sd3_clk_cfg;
68 break;
69 default:
70 printf("Wrong mmc number %d\n", sdc_no);
71 return -1;
72 }
73 mmchost->mmc_no = sdc_no;
74
75 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
76 if (cd_pin >= 0) {
77 ret = gpio_request(cd_pin, "mmc_cd");
78 if (!ret) {
79 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
80 ret = gpio_direction_input(cd_pin);
81 }
82 }
83
84 return ret;
85}
86
87static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
88{
89 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
90
91 if (hz <= 24000000) {
92 pll = CCM_MMC_CTRL_OSCM24;
93 pll_hz = 24000000;
94 } else {
95#ifdef CONFIG_MACH_SUN9I
96 pll = CCM_MMC_CTRL_PLL_PERIPH0;
97 pll_hz = clock_get_pll4_periph0();
98#else
99 pll = CCM_MMC_CTRL_PLL6;
100 pll_hz = clock_get_pll6();
101#endif
102 }
103
104 div = pll_hz / hz;
105 if (pll_hz % hz)
106 div++;
107
108 n = 0;
109 while (div > 16) {
110 n++;
111 div = (div + 1) / 2;
112 }
113
114 if (n > 3) {
115 printf("mmc %u error cannot set clock to %u\n",
116 mmchost->mmc_no, hz);
117 return -1;
118 }
119
120
121 if (hz <= 400000) {
122 oclk_dly = 0;
123 sclk_dly = 0;
124 } else if (hz <= 25000000) {
125 oclk_dly = 0;
126 sclk_dly = 5;
127#ifdef CONFIG_MACH_SUN9I
128 } else if (hz <= 50000000) {
129 oclk_dly = 5;
130 sclk_dly = 4;
131 } else {
132
133 oclk_dly = 2;
134 sclk_dly = 4;
135#else
136 } else if (hz <= 50000000) {
137 oclk_dly = 3;
138 sclk_dly = 4;
139 } else {
140
141 oclk_dly = 1;
142 sclk_dly = 4;
143#endif
144 }
145
146 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
147 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
148 CCM_MMC_CTRL_M(div), mmchost->mclkreg);
149
150 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
151 mmchost->mmc_no, hz, pll_hz, 1u << n, div,
152 pll_hz / (1u << n) / div);
153
154 return 0;
155}
156
157static int mmc_clk_io_on(int sdc_no)
158{
159 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
160 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
161
162 debug("init mmc %d clock and io\n", sdc_no);
163
164
165 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
166
167#ifdef CONFIG_SUNXI_GEN_SUN6I
168
169 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
170#endif
171#if defined(CONFIG_MACH_SUN9I)
172
173 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
174 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
175#endif
176
177 return mmc_set_mod_clk(mmchost, 24000000);
178}
179
180static int mmc_update_clk(struct mmc *mmc)
181{
182 struct sunxi_mmc_host *mmchost = mmc->priv;
183 unsigned int cmd;
184 unsigned timeout_msecs = 2000;
185
186 cmd = SUNXI_MMC_CMD_START |
187 SUNXI_MMC_CMD_UPCLK_ONLY |
188 SUNXI_MMC_CMD_WAIT_PRE_OVER;
189 writel(cmd, &mmchost->reg->cmd);
190 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
191 if (!timeout_msecs--)
192 return -1;
193 udelay(1000);
194 }
195
196
197 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
198
199 return 0;
200}
201
202static int mmc_config_clock(struct mmc *mmc)
203{
204 struct sunxi_mmc_host *mmchost = mmc->priv;
205 unsigned rval = readl(&mmchost->reg->clkcr);
206
207
208 rval &= ~SUNXI_MMC_CLK_ENABLE;
209 writel(rval, &mmchost->reg->clkcr);
210 if (mmc_update_clk(mmc))
211 return -1;
212
213
214 if (mmc_set_mod_clk(mmchost, mmc->clock))
215 return -1;
216
217
218 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
219 writel(rval, &mmchost->reg->clkcr);
220
221
222 rval |= SUNXI_MMC_CLK_ENABLE;
223 writel(rval, &mmchost->reg->clkcr);
224 if (mmc_update_clk(mmc))
225 return -1;
226
227 return 0;
228}
229
230static void sunxi_mmc_set_ios(struct mmc *mmc)
231{
232 struct sunxi_mmc_host *mmchost = mmc->priv;
233
234 debug("set ios: bus_width: %x, clock: %d\n",
235 mmc->bus_width, mmc->clock);
236
237
238 if (mmc->clock && mmc_config_clock(mmc) != 0) {
239 mmchost->fatal_err = 1;
240 return;
241 }
242
243
244 if (mmc->bus_width == 8)
245 writel(0x2, &mmchost->reg->width);
246 else if (mmc->bus_width == 4)
247 writel(0x1, &mmchost->reg->width);
248 else
249 writel(0x0, &mmchost->reg->width);
250}
251
252static int sunxi_mmc_core_init(struct mmc *mmc)
253{
254 struct sunxi_mmc_host *mmchost = mmc->priv;
255
256
257 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
258 udelay(1000);
259
260 return 0;
261}
262
263static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
264{
265 struct sunxi_mmc_host *mmchost = mmc->priv;
266 const int reading = !!(data->flags & MMC_DATA_READ);
267 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
268 SUNXI_MMC_STATUS_FIFO_FULL;
269 unsigned i;
270 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
271 unsigned byte_cnt = data->blocksize * data->blocks;
272 unsigned timeout_msecs = byte_cnt >> 8;
273 if (timeout_msecs < 2000)
274 timeout_msecs = 2000;
275
276
277 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
278
279 for (i = 0; i < (byte_cnt >> 2); i++) {
280 while (readl(&mmchost->reg->status) & status_bit) {
281 if (!timeout_msecs--)
282 return -1;
283 udelay(1000);
284 }
285
286 if (reading)
287 buff[i] = readl(&mmchost->reg->fifo);
288 else
289 writel(buff[i], &mmchost->reg->fifo);
290 }
291
292 return 0;
293}
294
295static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
296 unsigned int done_bit, const char *what)
297{
298 struct sunxi_mmc_host *mmchost = mmc->priv;
299 unsigned int status;
300
301 do {
302 status = readl(&mmchost->reg->rint);
303 if (!timeout_msecs-- ||
304 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
305 debug("%s timeout %x\n", what,
306 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
307 return TIMEOUT;
308 }
309 udelay(1000);
310 } while (!(status & done_bit));
311
312 return 0;
313}
314
315static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
316 struct mmc_data *data)
317{
318 struct sunxi_mmc_host *mmchost = mmc->priv;
319 unsigned int cmdval = SUNXI_MMC_CMD_START;
320 unsigned int timeout_msecs;
321 int error = 0;
322 unsigned int status = 0;
323 unsigned int bytecnt = 0;
324
325 if (mmchost->fatal_err)
326 return -1;
327 if (cmd->resp_type & MMC_RSP_BUSY)
328 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
329 if (cmd->cmdidx == 12)
330 return 0;
331
332 if (!cmd->cmdidx)
333 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
334 if (cmd->resp_type & MMC_RSP_PRESENT)
335 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
336 if (cmd->resp_type & MMC_RSP_136)
337 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
338 if (cmd->resp_type & MMC_RSP_CRC)
339 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
340
341 if (data) {
342 if ((u32)(long)data->dest & 0x3) {
343 error = -1;
344 goto out;
345 }
346
347 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
348 if (data->flags & MMC_DATA_WRITE)
349 cmdval |= SUNXI_MMC_CMD_WRITE;
350 if (data->blocks > 1)
351 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
352 writel(data->blocksize, &mmchost->reg->blksz);
353 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
354 }
355
356 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
357 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
358 writel(cmd->cmdarg, &mmchost->reg->arg);
359
360 if (!data)
361 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
362
363
364
365
366
367
368 if (data) {
369 int ret = 0;
370
371 bytecnt = data->blocksize * data->blocks;
372 debug("trans data %d bytes\n", bytecnt);
373 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
374 ret = mmc_trans_data_by_cpu(mmc, data);
375 if (ret) {
376 error = readl(&mmchost->reg->rint) & \
377 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
378 error = TIMEOUT;
379 goto out;
380 }
381 }
382
383 error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
384 if (error)
385 goto out;
386
387 if (data) {
388 timeout_msecs = 120;
389 debug("cacl timeout %x msec\n", timeout_msecs);
390 error = mmc_rint_wait(mmc, timeout_msecs,
391 data->blocks > 1 ?
392 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
393 SUNXI_MMC_RINT_DATA_OVER,
394 "data");
395 if (error)
396 goto out;
397 }
398
399 if (cmd->resp_type & MMC_RSP_BUSY) {
400 timeout_msecs = 2000;
401 do {
402 status = readl(&mmchost->reg->status);
403 if (!timeout_msecs--) {
404 debug("busy timeout\n");
405 error = TIMEOUT;
406 goto out;
407 }
408 udelay(1000);
409 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
410 }
411
412 if (cmd->resp_type & MMC_RSP_136) {
413 cmd->response[0] = readl(&mmchost->reg->resp3);
414 cmd->response[1] = readl(&mmchost->reg->resp2);
415 cmd->response[2] = readl(&mmchost->reg->resp1);
416 cmd->response[3] = readl(&mmchost->reg->resp0);
417 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
418 cmd->response[3], cmd->response[2],
419 cmd->response[1], cmd->response[0]);
420 } else {
421 cmd->response[0] = readl(&mmchost->reg->resp0);
422 debug("mmc resp 0x%08x\n", cmd->response[0]);
423 }
424out:
425 if (error < 0) {
426 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
427 mmc_update_clk(mmc);
428 }
429 writel(0xffffffff, &mmchost->reg->rint);
430 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
431 &mmchost->reg->gctrl);
432
433 return error;
434}
435
436static int sunxi_mmc_getcd(struct mmc *mmc)
437{
438 struct sunxi_mmc_host *mmchost = mmc->priv;
439 int cd_pin;
440
441 cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
442 if (cd_pin < 0)
443 return 1;
444
445 return !gpio_get_value(cd_pin);
446}
447
448int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc)
449{
450 char *buf = malloc(512);
451 int valid_signature = 0;
452
453 if (buf == NULL)
454 panic("Failed to allocate memory\n");
455
456 if (mmc_getcd(mmc) && mmc_init(mmc) == 0 &&
457 mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 &&
458 strncmp(&buf[4], "eGON.BT0", 8) == 0)
459 valid_signature = 1;
460
461 free(buf);
462 return valid_signature;
463}
464
465static const struct mmc_ops sunxi_mmc_ops = {
466 .send_cmd = sunxi_mmc_send_cmd,
467 .set_ios = sunxi_mmc_set_ios,
468 .init = sunxi_mmc_core_init,
469 .getcd = sunxi_mmc_getcd,
470};
471
472struct mmc *sunxi_mmc_init(int sdc_no)
473{
474 struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
475
476 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
477
478 cfg->name = "SUNXI SD/MMC";
479 cfg->ops = &sunxi_mmc_ops;
480
481 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
482 cfg->host_caps = MMC_MODE_4BIT;
483#ifdef CONFIG_MACH_SUN50I
484 if (sdc_no == 2)
485 cfg->host_caps = MMC_MODE_8BIT;
486#endif
487 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
488 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
489
490 cfg->f_min = 400000;
491 cfg->f_max = 52000000;
492
493 if (mmc_resource_init(sdc_no) != 0)
494 return NULL;
495
496 mmc_clk_io_on(sdc_no);
497
498 return mmc_create(cfg, &mmc_host[sdc_no]);
499}
500
