LXR uboot/drivers/net/fm/t2080.c

   1/*
   2 * Copyright 2012 Freescale Semiconductor, Inc.
   3 *
   4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <phy.h>
  11#include <fm_eth.h>
  12#include <asm/immap_85xx.h>
  13#include <asm/fsl_serdes.h>
  14
  15u32 port_to_devdisr[] = {
  16        [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  17        [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  18        [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  19        [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  20        [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  21        [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
  22        [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
  23        [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
  24        [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
  25        [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
  26        [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
  27        [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
  28};
  29
  30static int is_device_disabled(enum fm_port port)
  31{
  32        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  33        u32 devdisr2 = in_be32(&gur->devdisr2);
  34
  35        return port_to_devdisr[port] & devdisr2;
  36}
  37
  38void fman_disable_port(enum fm_port port)
  39{
  40        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  41
  42        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  43}
  44
  45phy_interface_t fman_port_enet_if(enum fm_port port)
  46{
  47        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  49
  50        if (is_device_disabled(port))
  51                return PHY_INTERFACE_MODE_NONE;
  52
  53        if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
  54            ((is_serdes_configured(XAUI_FM1_MAC9))      ||
  55             (is_serdes_configured(XFI_FM1_MAC9))       ||
  56             (is_serdes_configured(XFI_FM1_MAC10))))
  57                return PHY_INTERFACE_MODE_XGMII;
  58
  59        if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
  60            ((is_serdes_configured(XFI_FM1_MAC1))       ||
  61             (is_serdes_configured(XFI_FM1_MAC2))))
  62                return PHY_INTERFACE_MODE_XGMII;
  63
  64        if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  65                FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
  66                return PHY_INTERFACE_MODE_RGMII;
  67
  68        if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  69                FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
  70                return PHY_INTERFACE_MODE_RGMII;
  71
  72        if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  73                FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
  74                return PHY_INTERFACE_MODE_RGMII;
  75
  76        switch (port) {
  77        case FM1_DTSEC1:
  78        case FM1_DTSEC2:
  79        case FM1_DTSEC3:
  80        case FM1_DTSEC4:
  81        case FM1_DTSEC5:
  82        case FM1_DTSEC6:
  83        case FM1_DTSEC9:
  84        case FM1_DTSEC10:
  85                if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  86                        return PHY_INTERFACE_MODE_SGMII;
  87                break;
  88        default:
  89                return PHY_INTERFACE_MODE_NONE;
  90        }
  91
  92        return PHY_INTERFACE_MODE_NONE;
  93}
  94