1/* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M54451EVB_H 15#define _M54451EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21#define CONFIG_M54451EVB /* M54451EVB board */ 22 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_MCFUART 26#define CONFIG_SYS_UART_PORT (0) 27#define CONFIG_BAUDRATE 115200 28 29#undef CONFIG_WATCHDOG 30 31#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33/* 34 * BOOTP options 35 */ 36#define CONFIG_BOOTP_BOOTFILESIZE 37#define CONFIG_BOOTP_BOOTPATH 38#define CONFIG_BOOTP_GATEWAY 39#define CONFIG_BOOTP_HOSTNAME 40 41/* Command line configuration */ 42#define CONFIG_CMD_DATE 43#undef CONFIG_CMD_JFFS2 44#define CONFIG_CMD_REGINFO 45 46/* Network configuration */ 47#define CONFIG_MCFFEC 48#ifdef CONFIG_MCFFEC 49# define CONFIG_MII 1 50# define CONFIG_MII_INIT 1 51# define CONFIG_SYS_DISCOVER_PHY 52# define CONFIG_SYS_RX_ETH_BUFFER 8 53# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 55# define CONFIG_SYS_FEC0_PINMUX 0 56# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 57# define MCFFEC_TOUT_LOOP 50000 58 59# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 60# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 61# define CONFIG_ETHPRIME "FEC0" 62# define CONFIG_IPADDR 192.162.1.2 63# define CONFIG_NETMASK 255.255.255.0 64# define CONFIG_SERVERIP 192.162.1.1 65# define CONFIG_GATEWAYIP 192.162.1.1 66 67/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 68# ifndef CONFIG_SYS_DISCOVER_PHY 69# define FECDUPLEX FULL 70# define FECSPEED _100BASET 71# else 72# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 73# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74# endif 75# endif /* CONFIG_SYS_DISCOVER_PHY */ 76#endif 77 78#define CONFIG_HOSTNAME M54451EVB 79#ifdef CONFIG_SYS_STMICRO_BOOT 80/* ST Micro serial flash */ 81#define CONFIG_SYS_LOAD_ADDR2 0x40010007 82#define CONFIG_EXTRA_ENV_SETTINGS \ 83 "netdev=eth0\0" \ 84 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 85 "loadaddr=0x40010000\0" \ 86 "sbfhdr=sbfhdr.bin\0" \ 87 "uboot=u-boot.bin\0" \ 88 "load=tftp ${loadaddr} ${sbfhdr};" \ 89 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 90 "upd=run load; run prog\0" \ 91 "prog=sf probe 0:1 1000000 3;" \ 92 "sf erase 0 30000;" \ 93 "sf write ${loadaddr} 0 30000;" \ 94 "save\0" \ 95 "" 96#else 97#define CONFIG_SYS_UBOOT_END 0x3FFFF 98#define CONFIG_EXTRA_ENV_SETTINGS \ 99 "netdev=eth0\0" \ 100 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 101 "loadaddr=40010000\0" \ 102 "u-boot=u-boot.bin\0" \ 103 "load=tftp ${loadaddr) ${u-boot}\0" \ 104 "upd=run load; run prog\0" \ 105 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 106 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 107 "cp.b ${loadaddr} 0 ${filesize};" \ 108 "save\0" \ 109 "" 110#endif 111 112/* Realtime clock */ 113#define CONFIG_MCFRTC 114#undef RTC_DEBUG 115#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 116 117/* Timer */ 118#define CONFIG_MCFTMR 119#undef CONFIG_MCFPIT 120 121/* I2c */ 122#define CONFIG_SYS_I2C 123#define CONFIG_SYS_I2C_FSL 124#define CONFIG_SYS_FSL_I2C_SPEED 80000 125#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 126#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 127#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 128 129/* DSPI and Serial Flash */ 130#define CONFIG_CF_SPI 131#define CONFIG_CF_DSPI 132#define CONFIG_SERIAL_FLASH 133#define CONFIG_HARD_SPI 134#define CONFIG_SYS_SBFHDR_SIZE 0x7 135#ifdef CONFIG_CMD_SPI 136 137# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 138 DSPI_CTAR_PCSSCK_1CLK | \ 139 DSPI_CTAR_PASC(0) | \ 140 DSPI_CTAR_PDT(0) | \ 141 DSPI_CTAR_CSSCK(0) | \ 142 DSPI_CTAR_ASC(0) | \ 143 DSPI_CTAR_DT(1)) 144# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 145# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 146#endif 147 148/* Input, PCI, Flexbus, and VCO */ 149#define CONFIG_EXTRA_CLOCK 150 151#define CONFIG_PRAM 2048 /* 2048 KB */ 152 153#define CONFIG_SYS_LONGHELP /* undef to save memory */ 154 155#if defined(CONFIG_CMD_KGDB) 156#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 157#else 158#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 159#endif 160#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 161#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 162#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 163 164#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 165 166#define CONFIG_SYS_MBAR 0xFC000000 167 168/* 169 * Low Level Configuration Settings 170 * (address mappings, register initial values, etc.) 171 * You should know what you are doing if you make changes here. 172 */ 173 174/*----------------------------------------------------------------------- 175 * Definitions for initial stack pointer and data area (in DPRAM) 176 */ 177#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 178#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 179#define CONFIG_SYS_INIT_RAM_CTRL 0x221 180#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 182#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 183 184/*----------------------------------------------------------------------- 185 * Start addresses for the final memory configuration 186 * (Set up by the startup code) 187 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 188 */ 189#define CONFIG_SYS_SDRAM_BASE 0x40000000 190#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 191#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 192#define CONFIG_SYS_SDRAM_CFG2 0x57670000 193#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 194#define CONFIG_SYS_SDRAM_EMOD 0x80810000 195#define CONFIG_SYS_SDRAM_MODE 0x008D0000 196#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 197 198#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 199#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 200 201#ifdef CONFIG_CF_SBF 202# define CONFIG_SERIAL_BOOT 203# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 204#else 205# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 206#endif 207#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 208#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 209 210/* Reserve 256 kB for malloc() */ 211#define CONFIG_SYS_MALLOC_LEN (256 << 10) 212/* 213 * For booting Linux, the board info and command line data 214 * have to be in the first 8 MB of memory, since this is 215 * the maximum mapped by the Linux kernel during initialization ?? 216 */ 217/* Initial Memory map for Linux */ 218#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 219 220/* Configuration for environment 221 * Environment is not embedded in u-boot. First time runing may have env 222 * crc error warning if there is no correct environment on the flash. 223 */ 224#if defined(CONFIG_SYS_STMICRO_BOOT) 225# define CONFIG_ENV_IS_IN_SPI_FLASH 1 226# define CONFIG_ENV_SPI_CS 1 227# define CONFIG_ENV_OFFSET 0x20000 228# define CONFIG_ENV_SIZE 0x2000 229# define CONFIG_ENV_SECT_SIZE 0x10000 230#else 231# define CONFIG_ENV_IS_IN_FLASH 1 232# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 233# define CONFIG_ENV_SIZE 0x2000 234# define CONFIG_ENV_SECT_SIZE 0x20000 235#endif 236#undef CONFIG_ENV_OVERWRITE 237 238/* FLASH organization */ 239#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 240 241#define CONFIG_SYS_FLASH_CFI 242#ifdef CONFIG_SYS_FLASH_CFI 243 244# define CONFIG_FLASH_CFI_DRIVER 1 245# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 246# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 247# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 248# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 249# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 250# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 251# define CONFIG_SYS_FLASH_CHECKSUM 252# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 253 254#endif 255 256/* 257 * This is setting for JFFS2 support in u-boot. 258 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 259 */ 260#ifdef CONFIG_CMD_JFFS2 261# define CONFIG_JFFS2_DEV "nor0" 262# define CONFIG_JFFS2_PART_SIZE 0x01000000 263# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 264#endif 265 266/* Cache Configuration */ 267#define CONFIG_SYS_CACHELINE_SIZE 16 268 269#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 270 CONFIG_SYS_INIT_RAM_SIZE - 8) 271#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - 4) 273#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 274#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 275#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 276 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 277 CF_ACR_EN | CF_ACR_SM_ALL) 278#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 279 CF_CACR_ICINVA | CF_CACR_EUSP) 280#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 281 CF_CACR_DEC | CF_CACR_DDCM_P | \ 282 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 283 284/*----------------------------------------------------------------------- 285 * Memory bank definitions 286 */ 287/* 288 * CS0 - NOR Flash 16MB 289 * CS1 - Available 290 * CS2 - Available 291 * CS3 - Available 292 * CS4 - Available 293 * CS5 - Available 294 */ 295 296 /* Flash */ 297#define CONFIG_SYS_CS0_BASE 0x00000000 298#define CONFIG_SYS_CS0_MASK 0x00FF0001 299#define CONFIG_SYS_CS0_CTRL 0x00004D80 300 301#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 302 303#endif /* _M54451EVB_H */ 304