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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_PMC405DE 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15#define CONFIG_DISPLAY_BOARDINFO
16
17#define CONFIG_BOARD_EARLY_INIT_F 1
18#define CONFIG_MISC_INIT_R 1
19#define CONFIG_BOARD_TYPES 1
20
21#define CONFIG_SYS_CLK_FREQ 33330000
22
23#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 3
25
26#undef CONFIG_BOOTARGS
27#undef CONFIG_BOOTCOMMAND
28
29#define CONFIG_PREBOOT
30
31#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
32
33#define CONFIG_HAS_ETH1
34
35#define CONFIG_PPC4xx_EMAC
36#define CONFIG_MII 1
37#define CONFIG_PHY_ADDR 1
38#define CONFIG_PHY1_ADDR 2
39
40#define CONFIG_SYS_RX_ETH_BUFFER 16
41
42
43
44
45#define CONFIG_BOOTP_SUBNETMASK
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_DNS
50#define CONFIG_BOOTP_DNS2
51#define CONFIG_BOOTP_SEND_HOSTNAME
52
53
54
55
56#define CONFIG_CMD_BSP
57#define CONFIG_CMD_CHIP_CONFIG
58#define CONFIG_CMD_DATE
59#define CONFIG_CMD_EEPROM
60#define CONFIG_CMD_IRQ
61#define CONFIG_CMD_PCI
62
63#undef CONFIG_WATCHDOG
64#define CONFIG_SDRAM_BANK0 1
65#define CONFIG_PRAM 0
66
67
68
69
70#define CONFIG_SYS_LONGHELP
71
72#define CONFIG_SYS_CBSIZE 256
73#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
74#define CONFIG_SYS_MAXARGS 16
75#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
76
77#define CONFIG_SYS_DEVICE_NULLDEV 1
78#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
79
80#define CONFIG_SYS_MEMTEST_START 0x0100000
81#define CONFIG_SYS_MEMTEST_END 0x3000000
82
83#define CONFIG_CONS_INDEX 2
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
86#define CONFIG_SYS_NS16550_CLK get_serial_clock()
87
88#undef CONFIG_SYS_EXT_SERIAL_CLOCK
89#define CONFIG_SYS_BASE_BAUD 691200
90
91#define CONFIG_SYS_LOAD_ADDR 0x100000
92#define CONFIG_SYS_EXTBDINFO 1
93
94#define CONFIG_CMDLINE_EDITING 1
95#define CONFIG_MX_CYCLIC 1
96#define CONFIG_ZERO_BOOTDELAY_CHECK
97#define CONFIG_VERSION_VARIABLE 1
98
99
100
101
102#define PCI_HOST_ADAPTER 0
103#define PCI_HOST_FORCE 1
104#define PCI_HOST_AUTO 2
105
106#define CONFIG_PCI
107#define CONFIG_PCI_INDIRECT_BRIDGE
108#define CONFIG_PCI_HOST PCI_HOST_AUTO
109#define CONFIG_PCI_PNP
110
111#define CONFIG_PCI_SCAN_SHOW
112
113
114
115
116#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
117#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e
118#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f
119#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
120#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
121
122#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
123#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
124
125#define CONFIG_SYS_PCI_PTM1LA 0x00000000
126#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
127#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
128#define CONFIG_SYS_PCI_PTM2LA 0xef000000
129#define CONFIG_SYS_PCI_PTM2MS 0xff000001
130#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
131
132#define CONFIG_PCI_4xx_PTM_OVERWRITE 1
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134
135
136
137
138
139#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
140
141
142
143#define CONFIG_SYS_FLASH_CFI 1
144#define CONFIG_FLASH_CFI_DRIVER 1
145
146#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
147
148#define CONFIG_SYS_MAX_FLASH_BANKS 1
149#define CONFIG_SYS_MAX_FLASH_SECT 512
150
151#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500
153
154#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
155#define CONFIG_SYS_FLASH_PROTECTION 1
156
157#define CONFIG_SYS_FLASH_EMPTY_INFO 1
158#define CONFIG_SYS_FLASH_QUIET_TEST 1
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160
161
162
163
164
165#define CONFIG_SYS_SDRAM_BASE 0x00000000
166#define CONFIG_SYS_FLASH_BASE 0xfe000000
167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
168#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
169#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
170
171
172
173
174#define CONFIG_ENV_IS_IN_EEPROM 1
175#define CONFIG_ENV_OFFSET 0x100
176#define CONFIG_ENV_SIZE 0x700
177
178
179
180
181#define CONFIG_SYS_I2C
182#define CONFIG_SYS_I2C_PPC4XX
183#define CONFIG_SYS_I2C_PPC4XX_CH0
184#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
185#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
186
187#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
188#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
189
190#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
191#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
192
193
194#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
195#define CONFIG_SYS_EEPROM_WREN 1
196
197#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
198#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
199#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
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201
202
203
204#define CONFIG_RTC_RX8025
205
206
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209
210
211#define CONFIG_SYS_EBC_PB0AP 0x03017200
212#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
213
214
215#define CONFIG_SYS_CPLD_BASE 0xef000000
216#define CONFIG_SYS_EBC_PB1AP 0x00800000
217#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
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219
220
221
222
223#define CONFIG_SYS_TEMP_STACK_OCM 1
224
225
226#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
227#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
228
229#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
230
231#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
232
233#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
234 GENERATED_GBL_DATA_SIZE)
235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
236
237
238
239
240#define CONFIG_SYS_4xx_GPIO_TABLE { \
241{ \
242 \
243{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
244{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
245{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
246{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
247{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
248{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
249{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
250{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
251{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
252{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
253{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
254{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
255{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
256{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
257{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
258{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
259{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
260{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
261{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
262{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
263{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
264{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
265{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
266{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
267{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
268{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
269{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
270{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
271{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
272{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
273{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
274{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
275} \
276}
277
278#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1)
279#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
280#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5)
281#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6)
282#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7)
283#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8)
284#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9)
285#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11)
286#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12)
287#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13)
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291
292
293#undef CONFIG_SYS_FCPU333MHZ
294#define CONFIG_SYS_FCPU266MHZ
295#undef CONFIG_SYS_FCPU133MHZ
296
297#if defined(CONFIG_SYS_FCPU333MHZ)
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303
304
305#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
306 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
307 PLL_MALDIV_1 | PLL_PCIDIV_2)
308#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
309 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
310 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
311#endif
312
313#if defined(CONFIG_SYS_FCPU266MHZ)
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320
321#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
322 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
323 PLL_MALDIV_1 | PLL_PCIDIV_3)
324#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
325 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
326 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
327#endif
328
329#if defined(CONFIG_SYS_FCPU133MHZ)
330
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335
336
337#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
338 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
339 PLL_MALDIV_1 | PLL_PCIDIV_3)
340#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
341 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
342 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
343#endif
344
345#endif
346