1/* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * Configuration settings for the MX31ADS Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __CONFIG_H 10#define __CONFIG_H 11 12#include <asm/arch/imx-regs.h> 13 14 /* High Level Configuration Options */ 15#define CONFIG_MX31 1 /* This is a mx31 */ 16 17#define CONFIG_DISPLAY_CPUINFO 18#define CONFIG_DISPLAY_BOARDINFO 19 20#define CONFIG_SYS_TEXT_BASE 0xA0000000 21 22#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 23 24#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 25#define CONFIG_SETUP_MEMORY_TAGS 1 26#define CONFIG_INITRD_TAG 1 27 28/* 29 * Size of malloc() pool 30 */ 31#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 32 33/* 34 * Hardware drivers 35 */ 36 37#define CONFIG_MXC_UART 38#define CONFIG_MXC_UART_BASE UART1_BASE 39 40#define CONFIG_HARD_SPI 1 41#define CONFIG_MXC_SPI 1 42#define CONFIG_DEFAULT_SPI_BUS 1 43#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 44#define CONFIG_MXC_GPIO 45 46/* PMIC Controller */ 47#define CONFIG_POWER 48#define CONFIG_POWER_SPI 49#define CONFIG_POWER_FSL 50#define CONFIG_FSL_PMIC_BUS 1 51#define CONFIG_FSL_PMIC_CS 0 52#define CONFIG_FSL_PMIC_CLK 1000000 53#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 54#define CONFIG_FSL_PMIC_BITLEN 32 55#define CONFIG_RTC_MC13XXX 56 57/* allow to overwrite serial and ethaddr */ 58#define CONFIG_ENV_OVERWRITE 59#define CONFIG_CONS_INDEX 1 60#define CONFIG_BAUDRATE 115200 61 62/*********************************************************** 63 * Command definition 64 ***********************************************************/ 65#define CONFIG_CMD_DATE 66 67#define CONFIG_BOOTDELAY 3 68 69#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 70 71#define CONFIG_EXTRA_ENV_SETTINGS \ 72 "netdev=eth0\0" \ 73 "uboot_addr=0xa0000000\0" \ 74 "uboot=mx31ads/u-boot.bin\0" \ 75 "kernel=mx31ads/uImage\0" \ 76 "nfsroot=/opt/eldk/arm\0" \ 77 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 78 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 79 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 80 "bootcmd=run bootcmd_net\0" \ 81 "bootcmd_net=run bootargs_base bootargs_nfs; " \ 82 "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 83 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 84 "protect off ${uboot_addr} 0xa003ffff; " \ 85 "erase ${uboot_addr} 0xa003ffff; " \ 86 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 87 "setenv filesize; saveenv\0" 88 89#define CONFIG_CS8900 90#define CONFIG_CS8900_BASE 0xb4020300 91#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 92 93/* 94 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 95 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 96 * controller inverted. The controller is capable of detecting and correcting 97 * this, but it needs 4 network packets for that. Which means, at startup, you 98 * will not receive answers to the first 4 packest, unless there have been some 99 * broadcasts on the network, or your board is on a hub. Reducing the ARP 100 * timeout from default 5 seconds to 200ms we speed up the initial TFTP 101 * transfer, should the user wish one, significantly. 102 */ 103#define CONFIG_ARP_TIMEOUT 200UL 104 105/* 106 * Miscellaneous configurable options 107 */ 108#define CONFIG_SYS_LONGHELP /* undef to save memory */ 109#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110/* Print Buffer Size */ 111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 112#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 113#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 114 115#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 116#define CONFIG_SYS_MEMTEST_END 0x10000 117 118#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 119 120#define CONFIG_CMDLINE_EDITING 1 121 122/*----------------------------------------------------------------------- 123 * Physical Memory Map 124 */ 125#define CONFIG_NR_DRAM_BANKS 1 126#define PHYS_SDRAM_1 CSD0_BASE 127#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 128#define CONFIG_BOARD_EARLY_INIT_F 129 130#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 131#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 132#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 133#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 134 GENERATED_GBL_DATA_SIZE) 135#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 136 CONFIG_SYS_GBL_DATA_OFFSET) 137 138/*----------------------------------------------------------------------- 139 * FLASH and environment organization 140 */ 141#define CONFIG_SYS_FLASH_BASE CS0_BASE 142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 143#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 145#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 146 147#define CONFIG_ENV_IS_IN_FLASH 1 148#define CONFIG_ENV_SECT_SIZE (128 * 1024) 149#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 150#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 151 152/* Address and size of Redundant Environment Sector */ 153#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 154#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 155 156/*----------------------------------------------------------------------- 157 * CFI FLASH driver setup 158 */ 159#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 160#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 161#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 162#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 163#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 164 165/* 166 * JFFS2 partitions 167 */ 168#undef CONFIG_CMD_MTDPARTS 169#define CONFIG_JFFS2_DEV "nor0" 170 171#endif /* __CONFIG_H */ 172