LXR uboot/include/configs/neo.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12#define CONFIG_NEO              1       /*  on a Neo board */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16/*
  17 * Include common defines/options for all AMCC eval boards
  18 */
  19#define CONFIG_HOSTNAME         neo
  20#define CONFIG_IDENT_STRING     " neo 0.02"
  21#include "amcc-common.h"
  22
  23#define CONFIG_BOARD_EARLY_INIT_F
  24#define CONFIG_BOARD_EARLY_INIT_R
  25#define CONFIG_MISC_INIT_R
  26#define CONFIG_LAST_STAGE_INIT
  27
  28#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  29
  30/*
  31 * Configure PLL
  32 */
  33#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  34#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  35
  36/* new uImage format support */
  37#define CONFIG_FIT_DISABLE_SHA256
  38
  39#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  40
  41/*
  42 * Default environment variables
  43 */
  44#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  45        CONFIG_AMCC_DEF_ENV                                             \
  46        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  47        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  48        "kernel_addr=fc000000\0"                                        \
  49        "fdt_addr=fc1e0000\0"                                           \
  50        "ramdisk_addr=fc200000\0"                                       \
  51        ""
  52
  53#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  54#define CONFIG_HAS_ETH0
  55#define CONFIG_HAS_ETH1
  56#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  57#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  58
  59/*
  60 * Commands additional to the ones defined in amcc-common.h
  61 */
  62#define CONFIG_CMD_DTT
  63#undef CONFIG_CMD_DIAG
  64#undef CONFIG_CMD_EEPROM
  65#undef CONFIG_CMD_IRQ
  66
  67/*
  68 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  69 */
  70#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  71
  72/* SDRAM timings used in datasheet */
  73#define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
  74#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  75#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
  76#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  77#define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
  78
  79/*
  80 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  81 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  82 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  83 * The Linux BASE_BAUD define should match this configuration.
  84 *    baseBaud = cpuClock/(uartDivisor*16)
  85 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  86 * set Linux BASE_BAUD to 403200.
  87 */
  88#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  89#define CONFIG_SYS_NS16550_SERIAL
  90#define CONFIG_SYS_NS16550_REG_SIZE     1
  91#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  92
  93#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
  94#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
  95#define CONFIG_SYS_BASE_BAUD            691200
  96
  97/*
  98 * I2C stuff
  99 */
 100#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 101
 102/* RTC */
 103#define CONFIG_RTC_DS1337
 104#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 105
 106/* Temp sensor/hwmon/dtt */
 107#define CONFIG_DTT_LM63         1       /* National LM63        */
 108#define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 109#define CONFIG_DTT_PWM_LOOKUPTABLE      \
 110                { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 111#define CONFIG_DTT_TACH_LIMIT   0xa10
 112
 113/*
 114 * FLASH organization
 115 */
 116#define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 117#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 118
 119#define CONFIG_SYS_FLASH_BASE           0xFC000000
 120#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 121
 122#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 123#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 124
 125#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 126#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 127
 128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 129
 130#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 131#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 132
 133#ifdef CONFIG_ENV_IS_IN_FLASH
 134#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 135#define CONFIG_ENV_ADDR         0xFFF00000
 136#define CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector */
 137
 138/* Address and size of Redundant Environment Sector     */
 139#define CONFIG_ENV_ADDR_REDUND  0xFFF20000
 140#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 141#endif
 142
 143/*
 144 * PPC405 GPIO Configuration
 145 */
 146#define CONFIG_SYS_4xx_GPIO_TABLE { \
 147{ \
 148/* GPIO Core 0 */ \
 149{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 150{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 151{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 152{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 153{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 154{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3        */ \
 155{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4        */ \
 156{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5        */ \
 157{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 158{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk     */ \
 159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 160{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 166{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 167{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 168{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 169{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 170{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 171{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 172{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 173{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 174{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 175{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 177{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 178{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 179{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 180{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 181} \
 182}
 183
 184/*
 185 * Definitions for initial stack pointer and data area (in data cache)
 186 */
 187/* use on chip memory (OCM) for temperary stack until sdram is tested */
 188#define CONFIG_SYS_TEMP_STACK_OCM        1
 189
 190/* On Chip Memory location */
 191#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 192#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 193#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 194#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 195
 196#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 197#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 198
 199/*
 200 * External Bus Controller (EBC) Setup
 201 */
 202
 203/* Memory Bank 0 (NOR-FLASH) initialization                    */
 204#define CONFIG_SYS_EBC_PB0AP            0x92015480
 205#define CONFIG_SYS_EBC_PB0CR            0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 206
 207/* Memory Bank 1 (NVRAM) initialization                                        */
 208#define CONFIG_SYS_EBC_PB1AP            0x92015480
 209#define CONFIG_SYS_EBC_PB1CR            0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 210
 211/* Memory Bank 2 (FPGA) initialization                 */
 212#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 213#define CONFIG_SYS_EBC_PB2AP            0x92015480
 214#define CONFIG_SYS_EBC_PB2CR            0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 215
 216#define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 217
 218#define CONFIG_SYS_FPGA_COUNT           1
 219
 220#define CONFIG_SYS_FPGA_PTR \
 221        { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
 222
 223#define CONFIG_SYS_FPGA_COMMON
 224
 225/* Memory Bank 3 (Latches) initialization                      */
 226#define CONFIG_SYS_LATCH_BASE           0x7f200000
 227#define CONFIG_SYS_EBC_PB3AP            0x92015480
 228#define CONFIG_SYS_EBC_PB3CR            0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 229
 230#define CONFIG_SYS_LATCH0_RESET         0xffff
 231#define CONFIG_SYS_LATCH0_BOOT          0xffff
 232#define CONFIG_SYS_LATCH1_RESET         0xffbf
 233#define CONFIG_SYS_LATCH1_BOOT          0xffff
 234
 235#endif  /* __CONFIG_H */
 236