1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2006 6 * Eric Schumann, Phytec Messatechnik GmbH 7 * 8 * (C) Copyright 2009 9 * Jon Smirl <jonsmirl@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#ifndef __CONFIG_H 15#define __CONFIG_H 16 17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" 18 19/*----------------------------------------------------------------------------- 20High Level Configuration Options 21(easy to change) 22-----------------------------------------------------------------------------*/ 23#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ 24#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ 25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ 26 /* FEC configuration and IDE */ 27 28/* 29 * Valid values for CONFIG_SYS_TEXT_BASE are: 30 * 0xFFF00000 boot high (standard configuration) 31 * 0xFF000000 boot low 32 * 0x00100000 boot from RAM (for testing only) 33 */ 34#ifndef CONFIG_SYS_TEXT_BASE 35#define CONFIG_SYS_TEXT_BASE 0xFFF00000 36#endif 37 38#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ 39 40/*----------------------------------------------------------------------------- 41Serial console configuration 42-----------------------------------------------------------------------------*/ 43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ 44 /*define gps port conf. */ 45 /* register later on to */ 46 /*enable UART function! */ 47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 49 50/* 51 * Command line configuration. 52 */ 53#define CONFIG_CMD_DATE 54#define CONFIG_CMD_EEPROM 55#define CONFIG_CMD_JFFS2 56#define CONFIG_CMD_PCI 57 58#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ 59 60#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */ 61#define CONFIG_SYS_LOWBOOT 1 62#endif 63/* RAMBOOT will be defined automatically in memory section */ 64 65#define CONFIG_JFFS2_CMDLINE 66#define MTDIDS_DEFAULT "nor0=physmap-flash.0" 67#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ 68 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" 69 70/*----------------------------------------------------------------------------- 71Autobooting 72-----------------------------------------------------------------------------*/ 73#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 74#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ 75 /* even with bootdelay=0 */ 76#undef CONFIG_BOOTARGS 77 78#define CONFIG_PREBOOT "echo;" \ 79 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ 80 "mount root filesystem over NFS;" \ 81 "echo" 82 83#define CONFIG_EXTRA_ENV_SETTINGS \ 84 "netdev=eth0\0" \ 85 "uimage=uImage-pcm030\0" \ 86 "oftree=oftree-pcm030.dtb\0" \ 87 "jffs2=root-pcm030.jffs2\0" \ 88 "uboot=u-boot-pcm030.bin\0" \ 89 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ 90 " $(mtdparts) rw\0" \ 91 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ 92 " rootfstype=jffs2\0" \ 93 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ 94 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ 95 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 96 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ 97 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ 98 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ 99 "0xfff40000\0" \ 100 " cp.b 0x400000 0xff040000 $(filesize)\0" \ 101 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ 102 "cp.b 0x400000 0xff200000 $(filesize)\0" \ 103 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ 104 " cp.b 0x400000 0xfff40000 $(filesize)\0" \ 105 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ 106 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ 107 "unlock=yes\0" \ 108 "" 109 110#define CONFIG_BOOTCOMMAND "run bcmd_flash" 111 112/*-------------------------------------------------------------------------- 113IPB Bus clocking configuration. 114 ---------------------------------------------------------------------------*/ 115#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 116 117/*------------------------------------------------------------------------- 118 * PCI Mapping: 119 * 0x40000000 - 0x4fffffff - PCI Memory 120 * 0x50000000 - 0x50ffffff - PCI IO Space 121 * -----------------------------------------------------------------------*/ 122#define CONFIG_PCI 1 123#define CONFIG_PCI_PNP 1 124#define CONFIG_PCI_SCAN_SHOW 1 125#define CONFIG_PCI_MEM_BUS 0x40000000 126#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 127#define CONFIG_PCI_MEM_SIZE 0x10000000 128#define CONFIG_PCI_IO_BUS 0x50000000 129#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 130#define CONFIG_PCI_IO_SIZE 0x01000000 131#define CONFIG_SYS_XLB_PIPELINING 1 132 133/*--------------------------------------------------------------------------- 134 I2C configuration 135---------------------------------------------------------------------------*/ 136#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 137#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 138#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 139#define CONFIG_SYS_I2C_SLAVE 0x7F 140 141/*--------------------------------------------------------------------------- 142 EEPROM CAT24WC32 configuration 143---------------------------------------------------------------------------*/ 144#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ 145#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ 146#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 147#define CONFIG_SYS_EEPROM_SIZE 2048 148#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 149#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 150 151/*--------------------------------------------------------------------------- 152RTC configuration 153---------------------------------------------------------------------------*/ 154#define RTC 155#define CONFIG_RTC_PCF8563 1 156#define CONFIG_SYS_I2C_RTC_ADDR 0x51 157 158/*--------------------------------------------------------------------------- 159 Flash configuration 160---------------------------------------------------------------------------*/ 161 162#define CONFIG_SYS_FLASH_BASE 0xff000000 163#define CONFIG_SYS_FLASH_SIZE 0x01000000 164#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 165 166#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 167#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 168#define CONFIG_SYS_FLASH_EMPTY_INFO 169#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ 170#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 171 /* (= chip selects) */ 172#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 173 174/* 175 * Use also hardware protection. This seems required, as the BDI uses 176 * hardware protection. Without this, U-Boot can't work with this sectors, 177 * as its protection is software only by default 178 */ 179#define CONFIG_SYS_FLASH_PROTECTION 1 180 181/*--------------------------------------------------------------------------- 182 Environment settings 183---------------------------------------------------------------------------*/ 184 185/* pcm030 ships with environment is EEPROM by default */ 186#define CONFIG_ENV_IS_IN_EEPROM 1 187#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ 188 /*beginning of the EEPROM */ 189#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE 190 191#define CONFIG_ENV_OVERWRITE 1 192 193/*----------------------------------------------------------------------------- 194 Memory map 195-----------------------------------------------------------------------------*/ 196#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ 197 /* bootloader or debugger config */ 198#define CONFIG_SYS_SDRAM_BASE 0x00000000 199#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 200/* Use SRAM until RAM will be available */ 201#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 202#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */ 203 /* area in DPRAM */ 204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 205 GENERATED_GBL_DATA_SIZE) 206#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 207 208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 209#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 210# define CONFIG_SYS_RAMBOOT 1 211#endif 212 213#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 214#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 215#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 216 217/*----------------------------------------------------------------------------- 218 Ethernet configuration 219-----------------------------------------------------------------------------*/ 220#define CONFIG_MPC5xxx_FEC 1 221#define CONFIG_MPC5xxx_FEC_MII100 222#define CONFIG_PHY_ADDR 0x01 223 224/*--------------------------------------------------------------------------- 225 GPIO configuration 226 ---------------------------------------------------------------------------*/ 227 228/* GPIO port configuration 229 * 230 * Pin mapping: 231 * 232 * [29:31] = 01x 233 * PSC1_0 -> AC97 SDATA out 234 * PSC1_1 -> AC97 SDTA in 235 * PSC1_2 -> AC97 SYNC out 236 * PSC1_3 -> AC97 bitclock out 237 * PSC1_4 -> AC97 reset out 238 * 239 * [25:27] = 001 240 * PSC2_0 -> CAN 1 Tx out 241 * PSC2_1 -> CAN 1 Rx in 242 * PSC2_2 -> CAN 2 Tx out 243 * PSC2_3 -> CAN 2 Rx in 244 * PSC2_4 -> GPIO (claimed for ATA reset, active low) 245 * 246 * 247 * [20:23] = 1100 248 * PSC3_0 -> UART Tx out 249 * PSC3_1 -> UART Rx in 250 * PSC3_2 -> UART RTS (in/out FIXME) 251 * PSC3_3 -> UART CTS (in/out FIXME) 252 * PSC3_4 -> LocalPlus Bus CS6 \ 253 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] 254 * PSC3_6 -> dedicated SPI MOSI out (master case) 255 * PSC3_7 -> dedicated SPI MISO in (master case) 256 * PSC3_8 -> dedicated SPI SS out (master case) 257 * PSC3_9 -> dedicated SPI CLK out (master case) 258 * 259 * [18:19] = 01 260 * USB_0 -> USB OE out 261 * USB_1 -> USB Tx- out 262 * USB_2 -> USB Tx+ out 263 * USB_3 -> USB RxD (in/out FIXME) 264 * USB_4 -> USB Rx+ in 265 * USB_5 -> USB Rx- in 266 * USB_6 -> USB PortPower out 267 * USB_7 -> USB speed out 268 * USB_8 -> USB suspend (in/out FIXME) 269 * USB_9 -> USB overcurrent in 270 * 271 * [17] = 0 272 * USB differential mode 273 * 274 * [16] = 0 275 * PCI enabled 276 * 277 * [12:15] = 0101 278 * ETH_0 -> ETH Txen 279 * ETH_1 -> ETH TxD0 280 * ETH_2 -> ETH TxD1 281 * ETH_3 -> ETH TxD2 282 * ETH_4 -> ETH TxD3 283 * ETH_5 -> ETH Txerr 284 * ETH_6 -> ETH MDC 285 * ETH_7 -> ETH MDIO 286 * ETH_8 -> ETH RxDv 287 * ETH_9 -> ETH RxCLK 288 * ETH_10 -> ETH Collision 289 * ETH_11 -> ETH TxD 290 * ETH_12 -> ETH RxD0 291 * ETH_13 -> ETH RxD1 292 * ETH_14 -> ETH RxD2 293 * ETH_15 -> ETH RxD3 294 * ETH_16 -> ETH Rxerr 295 * ETH_17 -> ETH CRS 296 * 297 * [9:11] = 101 298 * PSC6_0 -> UART RxD in 299 * PSC6_1 -> UART CTS (in/out FIXME) 300 * PSC6_2 -> UART TxD out 301 * PSC6_3 -> UART RTS (in/out FIXME) 302 * 303 * [2:3/6:7] = 00/11 304 * TMR_0 -> ATA_CS0 out 305 * TMR_1 -> ATA_CS1 out 306 * TMR_2 -> GPIO 307 * TMR_3 -> GPIO 308 * TMR_4 -> GPIO 309 * TMR_5 -> GPIO 310 * TMR_6 -> GPIO 311 * TMR_7 -> GPIO 312 * I2C_0 -> I2C 1 Clock out 313 * I2C_1 -> I2C 1 IO in/out 314 * I2C_2 -> I2C 2 Clock out 315 * I2C_3 -> I2C 2 IO in/out 316 * 317 * [4] = 1 318 * PSC3_5 is used as CS7 319 * 320 * [5] = 1 321 * PSC3_4 is used as CS6 322 * 323 * [1] = 0 324 * gpio_wkup_7 is GPIO 325 * 326 * [0] = 0 327 * gpio_wkup_6 is GPIO 328 * 329 */ 330#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 331 332/*----------------------------------------------------------------------------- 333 Miscellaneous configurable options 334-------------------------------------------------------------------------------*/ 335#define CONFIG_SYS_LONGHELP /* undef to save memory */ 336 337#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 338 339#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 340#if defined(CONFIG_CMD_KGDB) 341#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 342#endif 343 344#if defined(CONFIG_CMD_KGDB) 345#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 346#else 347#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 348#endif 349#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 350 /* Print Buffer Size */ 351#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 352#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 353 354#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 355#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 356 357#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 358 359#define CONFIG_DISPLAY_BOARDINFO 1 360 361/*----------------------------------------------------------------------------- 362 Various low-level settings 363-----------------------------------------------------------------------------*/ 364#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 365#define CONFIG_SYS_HID0_FINAL HID0_ICE 366 367/* no burst access on the LPB */ 368#define CONFIG_SYS_CS_BURST 0x00000000 369/* one deadcycle for the 33MHz statemachine */ 370#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 371/* one additional waitstate for the 33MHz statemachine */ 372#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 373#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 374#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 375 376#define CONFIG_SYS_RESET_ADDRESS 0xff000000 377 378/*----------------------------------------------------------------------- 379 * USB stuff 380 *----------------------------------------------------------------------- 381 */ 382#define CONFIG_USB_CLOCK 0x0001BBBB 383#define CONFIG_USB_CONFIG 0x00001000 384 385/*--------------------------------------------------------------------------- 386 IDE/ATA stuff Supports IDE harddisk 387----------------------------------------------------------------------------*/ 388 389#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 390#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 391#undef CONFIG_IDE_LED /* LED for ide not supported */ 392#define CONFIG_SYS_ATA_CS_ON_TIMER01 393#define CONFIG_IDE_RESET 1 /* reset for ide supported */ 394#define CONFIG_IDE_PREINIT 395#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 396#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ 397#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 398#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 399/* Offset for data I/O */ 400#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 401/* Offset for normal register accesses */ 402#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 403/* Offset for alternate registers */ 404#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 405/* Interval between registers */ 406#define CONFIG_SYS_ATA_STRIDE 4 407#define CONFIG_ATAPI 1 408 409/* we enable IDE and FAT support, so we also need partition support */ 410#define CONFIG_DOS_PARTITION 1 411 412/* USB */ 413#define CONFIG_USB_OHCI 414#define CONFIG_USB_STORAGE 415 416/* pass open firmware flat tree */ 417#define OF_CPU "PowerPC,5200@0" 418#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN 419#define OF_SOC "soc5200@f0000000" 420#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" 421 422#endif /* __CONFIG_H */ 423