1/* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * 8 * Derived from OMAP3 work by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15#ifndef _OMAP4_H_ 16#define _OMAP4_H_ 17 18#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 19#include <asm/types.h> 20#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 21 22/* 23 * L4 Peripherals - L4 Wakeup and L4 Core now 24 */ 25#define OMAP44XX_L4_CORE_BASE 0x4A000000 26#define OMAP44XX_L4_WKUP_BASE 0x4A300000 27#define OMAP44XX_L4_PER_BASE 0x48000000 28 29#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 30#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 31#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 32#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 33 34/* CONTROL_ID_CODE */ 35#define CONTROL_ID_CODE 0x4A002204 36 37#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 38#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 39#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 40#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 41#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 42#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F 43#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F 44#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F 45 46/* UART */ 47#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 48#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 49#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 50 51/* General Purpose Timers */ 52#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 53#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 54#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 55 56/* Watchdog Timer2 - MPU watchdog */ 57#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 58 59/* 60 * Hardware Register Details 61 */ 62 63/* Watchdog Timer */ 64#define WD_UNLOCK1 0xAAAA 65#define WD_UNLOCK2 0x5555 66 67/* GP Timer */ 68#define TCLR_ST (0x1 << 0) 69#define TCLR_AR (0x1 << 1) 70#define TCLR_PRE (0x1 << 5) 71 72/* Control Module */ 73#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 74#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 75#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 76#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 77 78/* LPDDR2 IO regs */ 79#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 80#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 81#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 82#define LPDDR2IO_GR10_WD_MASK (3 << 17) 83#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F 84 85/* CONTROL_EFUSE_2 */ 86#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 87 88#define MMC1_PWRDNZ (1 << 26) 89#define MMC1_PBIASLITE_PWRDNZ (1 << 22) 90#define MMC1_PBIASLITE_VMODE (1 << 21) 91 92#ifndef __ASSEMBLY__ 93 94struct s32ktimer { 95 unsigned char res[0x10]; 96 unsigned int s32k_cr; /* 0x10 */ 97}; 98 99#define DEVICE_TYPE_SHIFT (0x8) 100#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 101#define DEVICE_GP 0x3 102 103#endif /* __ASSEMBLY__ */ 104 105/* 106 * Non-secure SRAM Addresses 107 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 108 * at 0x40304000(EMU base) so that our code works for both EMU and GP 109 */ 110#define NON_SECURE_SRAM_START 0x40304000 111#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 112#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 113/* base address for indirect vectors (internal boot mode) */ 114#define SRAM_ROM_VECT_BASE 0x4030D000 115 116/* ABB settings */ 117#define OMAP_ABB_SETTLING_TIME 50 118#define OMAP_ABB_CLOCK_CYCLES 16 119 120/* ABB tranxdone mask */ 121#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 122 123#define OMAP44XX_SAR_RAM_BASE 0x4a326000 124#define OMAP_REBOOT_REASON_OFFSET 0xA0C 125#define OMAP_REBOOT_REASON_SIZE 0x0F 126 127/* Boot parameters */ 128#ifndef __ASSEMBLY__ 129struct omap_boot_parameters { 130 unsigned int boot_message; 131 unsigned int boot_device_descriptor; 132 unsigned char boot_device; 133 unsigned char reset_reason; 134 unsigned char ch_flags; 135}; 136 137int omap_reboot_mode(char *mode, unsigned int length); 138int omap_reboot_mode_clear(void); 139int omap_reboot_mode_store(char *mode); 140#endif 141 142#endif 143