1/* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Tom Cubie <tangliang@allwinnertech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef _SUNXI_CPU_SUN4I_H 10#define _SUNXI_CPU_SUN4I_H 11 12#define SUNXI_SRAM_A1_BASE 0x00000000 13#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 14 15#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 16#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 17#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 18#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 19#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 20 21#ifdef CONFIG_MACH_SUN8I_A83T 22#define SUNXI_CPUCFG_BASE 0x01700000 23#endif 24 25#define SUNXI_SRAMC_BASE 0x01c00000 26#define SUNXI_DRAMC_BASE 0x01c01000 27#define SUNXI_DMA_BASE 0x01c02000 28#define SUNXI_NFC_BASE 0x01c03000 29#define SUNXI_TS_BASE 0x01c04000 30#define SUNXI_SPI0_BASE 0x01c05000 31#define SUNXI_SPI1_BASE 0x01c06000 32#define SUNXI_MS_BASE 0x01c07000 33#define SUNXI_TVD_BASE 0x01c08000 34#define SUNXI_CSI0_BASE 0x01c09000 35#define SUNXI_TVE0_BASE 0x01c0a000 36#define SUNXI_EMAC_BASE 0x01c0b000 37#define SUNXI_LCD0_BASE 0x01c0C000 38#define SUNXI_LCD1_BASE 0x01c0d000 39#define SUNXI_VE_BASE 0x01c0e000 40#define SUNXI_MMC0_BASE 0x01c0f000 41#define SUNXI_MMC1_BASE 0x01c10000 42#define SUNXI_MMC2_BASE 0x01c11000 43#define SUNXI_MMC3_BASE 0x01c12000 44#ifdef CONFIG_SUNXI_GEN_SUN4I 45#define SUNXI_USB0_BASE 0x01c13000 46#define SUNXI_USB1_BASE 0x01c14000 47#endif 48#define SUNXI_SS_BASE 0x01c15000 49#define SUNXI_HDMI_BASE 0x01c16000 50#define SUNXI_SPI2_BASE 0x01c17000 51#define SUNXI_SATA_BASE 0x01c18000 52#ifdef CONFIG_SUNXI_GEN_SUN4I 53#define SUNXI_PATA_BASE 0x01c19000 54#define SUNXI_ACE_BASE 0x01c1a000 55#define SUNXI_TVE1_BASE 0x01c1b000 56#define SUNXI_USB2_BASE 0x01c1c000 57#endif 58#ifdef CONFIG_SUNXI_GEN_SUN6I 59#ifdef CONFIG_MACH_SUN8I_H3 60#define SUNXI_USBPHY_BASE 0x01c19000 61#define SUNXI_USB0_BASE 0x01c1a000 62#define SUNXI_USB1_BASE 0x01c1b000 63#define SUNXI_USB2_BASE 0x01c1c000 64#define SUNXI_USB3_BASE 0x01c1d000 65#else 66#define SUNXI_USB0_BASE 0x01c19000 67#define SUNXI_USB1_BASE 0x01c1a000 68#define SUNXI_USB2_BASE 0x01c1b000 69#endif 70#endif 71#define SUNXI_CSI1_BASE 0x01c1d000 72#define SUNXI_TZASC_BASE 0x01c1e000 73#define SUNXI_SPI3_BASE 0x01c1f000 74 75#define SUNXI_CCM_BASE 0x01c20000 76#define SUNXI_INTC_BASE 0x01c20400 77#define SUNXI_PIO_BASE 0x01c20800 78#define SUNXI_TIMER_BASE 0x01c20c00 79#define SUNXI_SPDIF_BASE 0x01c21000 80#define SUNXI_AC97_BASE 0x01c21400 81#define SUNXI_IR0_BASE 0x01c21800 82#define SUNXI_IR1_BASE 0x01c21c00 83 84#define SUNXI_IIS_BASE 0x01c22400 85#define SUNXI_LRADC_BASE 0x01c22800 86#define SUNXI_AD_DA_BASE 0x01c22c00 87#define SUNXI_KEYPAD_BASE 0x01c23000 88#define SUNXI_TZPC_BASE 0x01c23400 89 90#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) 91/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 92#define SUNXI_SID_BASE 0x01c14200 93#else 94#define SUNXI_SID_BASE 0x01c23800 95#endif 96 97#define SUNXI_SJTAG_BASE 0x01c23c00 98 99#define SUNXI_TP_BASE 0x01c25000 100#define SUNXI_PMU_BASE 0x01c25400 101 102#ifdef CONFIG_MACH_SUN7I 103#define SUNXI_CPUCFG_BASE 0x01c25c00 104#endif 105 106#define SUNXI_UART0_BASE 0x01c28000 107#define SUNXI_UART1_BASE 0x01c28400 108#define SUNXI_UART2_BASE 0x01c28800 109#define SUNXI_UART3_BASE 0x01c28c00 110#define SUNXI_UART4_BASE 0x01c29000 111#define SUNXI_UART5_BASE 0x01c29400 112#define SUNXI_UART6_BASE 0x01c29800 113#define SUNXI_UART7_BASE 0x01c29c00 114#define SUNXI_PS2_0_BASE 0x01c2a000 115#define SUNXI_PS2_1_BASE 0x01c2a400 116 117#define SUNXI_TWI0_BASE 0x01c2ac00 118#define SUNXI_TWI1_BASE 0x01c2b000 119#define SUNXI_TWI2_BASE 0x01c2b400 120#ifdef CONFIG_MACH_SUN6I 121#define SUNXI_TWI3_BASE 0x01c0b800 122#endif 123#ifdef CONFIG_MACH_SUN7I 124#define SUNXI_TWI3_BASE 0x01c2b800 125#define SUNXI_TWI4_BASE 0x01c2c000 126#endif 127 128#define SUNXI_CAN_BASE 0x01c2bc00 129 130#define SUNXI_SCR_BASE 0x01c2c400 131 132#ifndef CONFIG_MACH_SUN6I 133#define SUNXI_GPS_BASE 0x01c30000 134#define SUNXI_MALI400_BASE 0x01c40000 135#define SUNXI_GMAC_BASE 0x01c50000 136#else 137#define SUNXI_GMAC_BASE 0x01c30000 138#endif 139 140#define SUNXI_DRAM_COM_BASE 0x01c62000 141#define SUNXI_DRAM_CTL0_BASE 0x01c63000 142#define SUNXI_DRAM_CTL1_BASE 0x01c64000 143#define SUNXI_DRAM_PHY0_BASE 0x01c65000 144#define SUNXI_DRAM_PHY1_BASE 0x01c66000 145 146#define SUNXI_GIC400_BASE 0x01c80000 147 148/* module sram */ 149#define SUNXI_SRAM_C_BASE 0x01d00000 150 151#define SUNXI_DE_FE0_BASE 0x01e00000 152#define SUNXI_DE_FE1_BASE 0x01e20000 153#define SUNXI_DE_BE0_BASE 0x01e60000 154#define SUNXI_DE_BE1_BASE 0x01e40000 155#define SUNXI_MP_BASE 0x01e80000 156#define SUNXI_AVG_BASE 0x01ea0000 157 158#define SUNXI_RTC_BASE 0x01f00000 159#define SUNXI_PRCM_BASE 0x01f01400 160 161#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T 162#define SUNXI_CPUCFG_BASE 0x01f01c00 163#endif 164 165#define SUNXI_R_TWI_BASE 0x01f02400 166#define SUNXI_R_UART_BASE 0x01f02800 167#define SUNXI_R_PIO_BASE 0x01f02c00 168#define SUN6I_P2WI_BASE 0x01f03400 169#define SUNXI_RSB_BASE 0x01f03400 170 171/* CoreSight Debug Module */ 172#define SUNXI_CSDM_BASE 0x3f500000 173 174#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 175 176#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 177 178#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 179 180/* SS bonding ids used for cpu identification */ 181#define SUNXI_SS_BOND_ID_A31 4 182#define SUNXI_SS_BOND_ID_A31S 5 183 184#ifndef __ASSEMBLY__ 185void sunxi_board_init(void); 186void sunxi_reset(void); 187int sunxi_get_ss_bonding_id(void); 188int sunxi_get_sid(unsigned int *sid); 189#endif /* __ASSEMBLY__ */ 190 191#endif /* _SUNXI_CPU_SUN4I_H */ 192