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6
7#include <common.h>
8#include <i2c.h>
9#include <spl.h>
10#include <asm/io.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/soc.h>
13
14#include "high_speed_env_spec.h"
15#include "board_env_spec.h"
16
17#define SERDES_VERION "2.1.5"
18#define ENDED_OK "High speed PHY - Ended Successfully\n"
19
20static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
21
22extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
23
24extern u8 rd78460gp_twsi_dev[];
25extern u8 db88f78xx0rev2_twsi_dev[];
26
27u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
28int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
29int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
30
31#define MV_BOARD_PEX_MODULE_ADDR 0x23
32#define MV_BOARD_PEX_MODULE_ID 1
33#define MV_BOARD_ETM_MODULE_ID 2
34
35#define PEX_MODULE_DETECT 1
36#define ETM_MODULE_DETECT 2
37
38#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
39#define PEX_CAPABILITY_GET(satr) (satr & 1)
40#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
41
42
43static int config_module;
44static int switch_module;
45
46
47static u32 board_id_get(void)
48{
49#if defined(CONFIG_DB_88F78X60)
50 return DB_88F78XX0_BP_ID;
51#elif defined(CONFIG_RD_88F78460_SERVER)
52 return RD_78460_SERVER_ID;
53#elif defined(CONFIG_RD_78460_SERVER_REV2)
54 return RD_78460_SERVER_REV2_ID;
55#elif defined(CONFIG_DB_78X60_PCAC)
56 return DB_78X60_PCAC_ID;
57#elif defined(CONFIG_DB_88F78X60_REV2)
58 return DB_88F78XX0_BP_REV2_ID;
59#elif defined(CONFIG_RD_78460_NAS)
60 return RD_78460_NAS_ID;
61#elif defined(CONFIG_DB_78X60_AMC)
62 return DB_78X60_AMC_ID;
63#elif defined(CONFIG_DB_78X60_PCAC_REV2)
64 return DB_78X60_PCAC_REV2_ID;
65#elif defined(CONFIG_DB_784MP_GP)
66 return DB_784MP_GP_ID;
67#elif defined(CONFIG_RD_78460_CUSTOMER)
68 return RD_78460_CUSTOMER_ID;
69#else
70
71
72
73
74 return 0;
75#endif
76}
77
78__weak u8 board_sat_r_get(u8 dev_num, u8 reg)
79{
80 u8 data;
81 u8 *dev;
82 u32 board_id = board_id_get();
83 int ret;
84
85 switch (board_id) {
86 case DB_78X60_AMC_ID:
87 case DB_78X60_PCAC_REV2_ID:
88 case RD_78460_CUSTOMER_ID:
89 case RD_78460_SERVER_ID:
90 case RD_78460_SERVER_REV2_ID:
91 case DB_78X60_PCAC_ID:
92 return (0x1 << 1) | 1;
93 case FPGA_88F78XX0_ID:
94 case RD_78460_NAS_ID:
95 return (0x0 << 1) | 1;
96 case DB_784MP_GP_ID:
97 dev = rd78460gp_twsi_dev;
98
99 break;
100 case DB_88F78XX0_BP_ID:
101 case DB_88F78XX0_BP_REV2_ID:
102 dev = db88f78xx0rev2_twsi_dev;
103 break;
104
105 default:
106 return 0;
107 }
108
109
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
111 ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
112 if (ret)
113 return MV_ERROR;
114
115 return data;
116}
117
118static int board_modules_scan(void)
119{
120 u8 val;
121 u32 board_id = board_id_get();
122 int ret;
123
124
125 if ((board_id == DB_88F78XX0_BP_ID) ||
126 (board_id == DB_88F78XX0_BP_REV2_ID)) {
127
128 config_module = 0;
129
130 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
131
132
133 ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
134 if (ret)
135 return MV_ERROR;
136
137 if (val == MV_BOARD_PEX_MODULE_ID)
138 config_module = PEX_MODULE_DETECT;
139 if (val == MV_BOARD_ETM_MODULE_ID)
140 config_module = ETM_MODULE_DETECT;
141 } else if (board_id == RD_78460_NAS_ID) {
142 switch_module = 0;
143 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
144 switch_module = 1;
145 }
146
147 return MV_OK;
148}
149
150u32 pex_max_unit_get(void)
151{
152
153
154
155
156
157 return MV_PEX_MAX_UNIT;
158}
159
160u32 pex_max_if_get(void)
161{
162
163
164
165
166
167 return MV_PEX_MAX_IF;
168}
169
170u8 board_cpu_freq_get(void)
171{
172 u32 sar;
173 u32 sar_msb;
174
175 sar = reg_read(MPP_SAMPLE_AT_RESET(0));
176 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
177 return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
178}
179
180__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
181{
182 u32 board_id;
183 u32 serdes_cfg_val = 0;
184
185 board_id = board_id_get();
186
187 switch (board_id) {
188 case DB_784MP_GP_ID:
189 serdes_cfg_val = 0;
190 break;
191 }
192
193 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
194}
195
196u16 ctrl_model_get(void)
197{
198
199
200
201
202#if defined(CONFIG_MV78230)
203 return MV_78230_DEV_ID;
204#elif defined(CONFIG_MV78260)
205 return MV_78260_DEV_ID;
206#else
207 return MV_78460_DEV_ID;
208#endif
209}
210
211u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
212{
213 if (line_num < 8)
214 return (info->line0_7 >> (line_num << 2)) & 0xF;
215 else
216 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
217}
218
219static int serdes_max_lines_get(void)
220{
221 switch (ctrl_model_get()) {
222 case MV_78230_DEV_ID:
223 return 7;
224 case MV_78260_DEV_ID:
225 return 12;
226 case MV_78460_DEV_ID:
227 return 16;
228 }
229
230 return 0;
231}
232
233int serdes_phy_config(void)
234{
235 int status = MV_OK;
236 u32 line_cfg;
237 u8 line_num;
238
239 u32 addr[16][11], val[16][11];
240 u8 pex_unit, pex_line_num;
241 u8 sgmii_port = 0;
242 u32 tmp;
243 u32 in_direct;
244 u8 max_serdes_lines;
245 MV_BIN_SERDES_CFG *info;
246 u8 satr11;
247 u8 sata_port;
248 u8 freq;
249 u8 device_rev;
250 u32 rx_high_imp_mode;
251 u16 ctrl_mode;
252 u32 pex_if;
253 u32 pex_if_num;
254
255
256
257
258 max_serdes_lines = serdes_max_lines_get();
259 if (max_serdes_lines == 0)
260 return MV_OK;
261
262 satr11 = board_sat_r_get(1, 1);
263 if ((u8) MV_ERROR == (u8) satr11)
264 return MV_ERROR;
265
266 board_modules_scan();
267 memset(addr, 0, sizeof(addr));
268 memset(val, 0, sizeof(val));
269
270
271 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
272 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
273 DEBUG_INIT_S("High speed PHY - Version: ");
274 DEBUG_INIT_S(SERDES_VERION);
275 DEBUG_INIT_S(" - 2nd boot - Skip\n");
276 return MV_OK;
277 }
278 DEBUG_INIT_S("High speed PHY - Version: ");
279 DEBUG_INIT_S(SERDES_VERION);
280 DEBUG_INIT_S(" (COM-PHY-V20)\n");
281
282
283
284
285 freq = board_cpu_freq_get();
286 device_rev = mv_ctrl_rev_get();
287
288 if (device_rev == 2) {
289 u32 cpu_avs;
290 u8 fabric_freq;
291 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
292 DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
293 cpu_avs &= ~(1 << 9);
294
295 if ((0x4 == freq) || (0xB == freq)) {
296 u32 tmp2;
297
298 tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
299 DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
300
301 tmp2 |= 0x0FF;
302 reg_write(CPU_AVS_CONTROL0_REG, tmp2);
303 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
304 cpu_avs |= (1 << 9);
305 cpu_avs |= (1 << 18);
306 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
307 SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
308 if ((0xB == freq) && (5 == fabric_freq)) {
309 u32 core_avs;
310
311 core_avs = reg_read(CORE_AVS_CONTROL_0REG);
312 DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
313
314
315
316
317
318 core_avs &= ~(0xff);
319 core_avs |= 0x0E;
320 reg_write(CORE_AVS_CONTROL_0REG, core_avs);
321 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
322
323 core_avs = reg_read(CORE_AVS_CONTROL_2REG);
324 DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
325 core_avs |= (1 << 9);
326 reg_write(CORE_AVS_CONTROL_2REG, core_avs);
327 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
328
329 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
330 DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
331 tmp2);
332 tmp2 |= 0x1;
333 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
334 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
335 tmp2);
336 }
337 }
338 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
339 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
340 }
341
342 info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
343 DEBUG_INIT_FULL_S("info->line0_7= 0x");
344 DEBUG_INIT_FULL_D(info->line0_7, 8);
345 DEBUG_INIT_FULL_S(" info->line8_15= 0x");
346 DEBUG_INIT_FULL_D(info->line8_15, 8);
347 DEBUG_INIT_FULL_S("\n");
348
349 if (info == NULL) {
350 DEBUG_INIT_S("Hight speed PHY Error #1\n");
351 return MV_ERROR;
352 }
353
354 if (config_module & ETM_MODULE_DETECT) {
355 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
356 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
357 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
358 info->pex_mode[1] = PEX_BUS_DISABLED;
359 mdelay(100);
360 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d);
361 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d);
362 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d);
363 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d);
364 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801);
365 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801);
366 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801);
367 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801);
368 reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF);
369 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF);
370 reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF);
371 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF);
372 reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800);
373 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800);
374 reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800);
375 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800);
376 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400);
377 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400);
378 reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400);
379 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400);
380 }
381
382
383 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
384 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
385 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
386 continue;
387
388
389 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
390 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
391
392
393 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
394 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
395 (0xC2 << 16) | 0x200);
396 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
397 (0xC2 << 16) | 0x200);
398 }
399
400
401 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
402 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
403 (0xC3 << 16) | 0x0F);
404 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
405 (0xC3 << 16) | 0x0F);
406 }
407
408 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
409 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
410 (0xC5 << 16) | 0x11F);
411 }
412
413
414
415
416
417 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
418 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
419 line_cfg = get_line_cfg(line_num, info);
420 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
421 continue;
422 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
423 continue;
424 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
425 switch (line_num) {
426 case 4:
427 case 6:
428 sata_port = 0;
429 break;
430 case 5:
431 sata_port = 1;
432 break;
433 default:
434 DEBUG_INIT_C
435 ("SATA port error for serdes line: ",
436 line_num, 2);
437 return MV_ERROR;
438 }
439 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
440 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
441 tmp &= ~((0x1ff << 5) | 0x7);
442 tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
443 (0x11 << 5) : 0x0;
444
445 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
446 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
447 }
448
449 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
450
451
452
453
454 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
455 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
456 tmp &= ~((0x1ff << 5) | 0x7);
457 tmp |= 0x660;
458 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
459 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
460 continue;
461 }
462
463 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
464 sgmii_port = 0;
465 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
466 sgmii_port = 1;
467 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
468 sgmii_port = 2;
469 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
470 sgmii_port = 3;
471 else
472 continue;
473
474 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
475 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
476 tmp &= ~((0x1ff << 5) | 0x7);
477 tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
478 (0x88 << 5) : (0x66 << 5));
479 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
480 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
481 }
482
483
484 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
485 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
486 line_cfg = get_line_cfg(line_num, info);
487 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
488
489 tmp = reg_read(QSGMII_CONTROL_1_REG);
490 DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
491 tmp |= (1 << 30);
492#ifdef ERRATA_GL_6572255
493 tmp |= (1 << 27);
494#endif
495 reg_write(QSGMII_CONTROL_1_REG, tmp);
496 DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
497 }
498 }
499
500
501 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
502 if (config_module & ETM_MODULE_DETECT) {
503 reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
504 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
505 } else {
506 reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
507 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
508 }
509 reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
510 DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
511
512
513 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
514 rx_high_imp_mode = 0x8080;
515 if (device_rev == 2)
516 rx_high_imp_mode |= 4;
517
518 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
519
520 DEBUG_INIT_FULL_S("SERDES ");
521 DEBUG_INIT_FULL_D_10(line_num, 2);
522 line_cfg = get_line_cfg(line_num, info);
523 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
524 DEBUG_INIT_FULL_S(" unconnected ***\n");
525 continue;
526 }
527 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
528 pex_unit = line_num >> 2;
529 pex_line_num = line_num % 4;
530 DEBUG_INIT_FULL_S(" - PEX unit ");
531 DEBUG_INIT_FULL_D_10(pex_unit, 1);
532 DEBUG_INIT_FULL_S(" line= ");
533 DEBUG_INIT_FULL_D_10(pex_line_num, 1);
534 DEBUG_INIT_FULL_S("\n");
535
536
537 if ((line_num > 7) &&
538 (info->pex_mode[3] == PEX_BUS_MODE_X8))
539
540 pex_unit = 3;
541
542 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
543 continue;
544
545
546
547
548
549
550
551
552
553
554
555 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
556 in_direct = (0x48 << 16) | (pex_line_num << 24) |
557 0x1000 | rx_high_imp_mode;
558 } else if ((info->pex_mode[pex_unit] ==
559 PEX_BUS_MODE_X4) && (pex_line_num == 0))
560 in_direct = (0x48 << 16) | (pex_line_num << 24) |
561 0x1000 | (rx_high_imp_mode & 0xff);
562 else
563 in_direct = 0;
564
565 if (in_direct) {
566 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
567 in_direct);
568 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
569 in_direct);
570 }
571
572 continue;
573 }
574
575 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
576
577
578
579
580 sata_port = line_num & 1;
581 DEBUG_INIT_FULL_S(" - SATA port ");
582 DEBUG_INIT_FULL_D_10(sata_port, 2);
583 DEBUG_INIT_FULL_S("\n");
584 reg_write(SATA_COMPHY_CTRL_REG(sata_port),
585 rx_high_imp_mode);
586 DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
587 rx_high_imp_mode);
588 continue;
589 }
590
591 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
592 DEBUG_INIT_FULL_S(" - QSGMII\n");
593 reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
594 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
595 rx_high_imp_mode);
596 continue;
597 }
598
599 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
600 sgmii_port = 0;
601 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
602 sgmii_port = 1;
603 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
604 sgmii_port = 2;
605 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
606 sgmii_port = 3;
607 else
608 continue;
609 DEBUG_INIT_FULL_S(" - SGMII port ");
610 DEBUG_INIT_FULL_D_10(sgmii_port, 2);
611 DEBUG_INIT_FULL_S("\n");
612 reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
613 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
614 rx_high_imp_mode);
615 }
616
617
618 DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
619 tmp = reg_read(SOC_CTRL_REG);
620 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
621 tmp &= 0x200;
622 if (info->pex_mode[0] == PEX_BUS_MODE_X1)
623 tmp |= PCIE0_QUADX1_EN;
624 if (info->pex_mode[1] == PEX_BUS_MODE_X1)
625 tmp |= PCIE1_QUADX1_EN;
626 if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
627 PEX_CLK_100MHZ_OFFSET) == 0x1)
628 tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
629
630 reg_write(SOC_CTRL_REG, tmp);
631 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
632
633
634 DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
635
636 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
637 line_cfg = get_line_cfg(line_num, info);
638
639 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
640
641
642
643
644
645
646 pex_unit = line_num >> 2;
647 pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
648 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
649 continue;
650
651
652 tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
653 DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
654 tmp |= (1 << 6);
655 reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
656 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
657
658 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
659 DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
660 tmp &= ~(0x3FF);
661 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
662 tmp |= (0x1 << 4);
663 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
664 tmp |= (0x4 << 4);
665 if (0 == PEX_CAPABILITY_GET(satr11))
666 tmp |= 0x1;
667 else
668 tmp |= 0x2;
669 DEBUG_INIT_FULL_S("Step 6.2: PEX ");
670 DEBUG_INIT_FULL_D(pex_if, 1);
671 DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
672 reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
673 DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
674
675
676
677
678
679 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
680 line_num += 3;
681 }
682 }
683
684
685
686
687
688
689 DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
690 tmp = reg_read(GEN_PURP_RES_2_REG);
691 DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
692
693 tmp &= 0xFFFF0000;
694 if (info->pex_mode[0] == PEX_BUS_MODE_X4)
695 tmp |= 0x0000000F;
696
697 if (info->pex_mode[1] == PEX_BUS_MODE_X4)
698 tmp |= 0x000000F0;
699
700 if (info->pex_mode[2] == PEX_BUS_MODE_X4)
701 tmp |= 0x00000F00;
702
703 if (info->pex_mode[3] == PEX_BUS_MODE_X4)
704 tmp |= 0x0000F000;
705
706 reg_write(GEN_PURP_RES_2_REG, tmp);
707 DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
708
709
710 DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
711
712
713 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
714
715
716 line_cfg = get_line_cfg(line_num, info);
717
718 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
719 continue;
720
721 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
722 pex_unit = line_num >> 2;
723 pex_line_num = line_num % 4;
724
725 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
726 continue;
727
728
729
730
731
732
733 if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
734 (0 == pex_line_num))
735 || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
736 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
737 (0x01 << 16) | (pex_line_num << 24) |
738 0xFC60);
739 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
740 (0x01 << 16) | (pex_line_num << 24)
741 | 0xFC60);
742
743
744
745
746
747
748 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
749 (0x02 << 16) | (1 << 31) |
750 (pex_line_num << 24));
751 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
752 (0x02 << 16) | (1 << 31) |
753 (pex_line_num << 24));
754 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
755 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
756 tmp &= ~(1 << 31);
757 tmp |= (1 << 8);
758 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
759 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
760
761
762 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
763 (0x81 << 16) | (1 << 31) |
764 (pex_line_num << 24));
765 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
766 (0x81 << 16) | (1 << 31) |
767 (pex_line_num << 24));
768 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
769 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
770 tmp &= ~(1 << 31);
771 tmp |= (3 << 9);
772 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
773 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
774 }
775
776 continue;
777 }
778
779 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
780
781
782
783
784 sata_port = line_num & 1;
785
786
787
788
789
790
791
792 reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
793 DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
794
795
796 reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
797 DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
798
799
800
801 reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
802 DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
803
804
805 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
806 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
807 tmp |= 7;
808 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
809 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
810
811 continue;
812 }
813
814 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
815
816
817
818
819 reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
820 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
821
822
823
824
825
826 reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
827 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
828
829
830
831
832
833 reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
834 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
835
836
837 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
838 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
839 tmp |= 7;
840 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
841 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
842 continue;
843 }
844
845 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
846 sgmii_port = 0;
847 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
848 sgmii_port = 1;
849 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
850 sgmii_port = 2;
851 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
852 sgmii_port = 3;
853 else
854 continue;
855
856
857
858
859
860 reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
861 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
862
863
864 reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
865 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
866
867
868 reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
869 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
870
871
872 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
873 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
874 tmp |= 7;
875 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
876 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
877
878 }
879
880
881 DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
882 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
883
884
885 line_cfg = get_line_cfg(line_num, info);
886
887 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
888 continue;
889
890 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
891 pex_unit = line_num >> 2;
892 pex_line_num = line_num % 4;
893 if (0 == pex_line_num) {
894 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
895 (0xC1 << 16) | 0x24);
896 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
897 (0xC1 << 16) | 0x24);
898 }
899 }
900 }
901
902
903
904 DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
905 mdelay(15);
906 tmp = 20;
907 while (tmp) {
908 status = MV_OK;
909 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
910 u32 tmp;
911 line_cfg = get_line_cfg(line_num, info);
912 if (line_cfg ==
913 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
914 continue;
915
916 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
917 continue;
918
919 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
920
921
922
923
924 sata_port = line_num & 1;
925
926 tmp =
927 reg_read(SATA_LP_PHY_EXT_STAT_REG
928 (sata_port));
929 DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
930 (sata_port), tmp);
931 if ((tmp & 0x7) != 0x7)
932 status = MV_ERROR;
933 continue;
934 }
935
936 if (line_cfg ==
937 serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
938 tmp = reg_read(SGMII_SERDES_STAT_REG(0));
939 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
940 if ((tmp & 0x7) != 0x7)
941 status = MV_ERROR;
942 continue;
943 }
944
945 if (line_cfg ==
946 serdes_cfg[line_num][SERDES_UNIT_SGMII0])
947 sgmii_port = 0;
948 else if (line_cfg ==
949 serdes_cfg[line_num][SERDES_UNIT_SGMII1])
950 sgmii_port = 1;
951 else if (line_cfg ==
952 serdes_cfg[line_num][SERDES_UNIT_SGMII2])
953 sgmii_port = 2;
954 else if (line_cfg ==
955 serdes_cfg[line_num][SERDES_UNIT_SGMII3])
956 sgmii_port = 3;
957 else
958 continue;
959
960 tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
961 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
962 if ((tmp & 0x7) != 0x7)
963 status = MV_ERROR;
964 }
965
966 if (status == MV_OK)
967 break;
968 mdelay(5);
969 tmp--;
970 }
971
972
973
974
975
976 DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
977 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
978 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
979 continue;
980 tmp =
981 reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
982 DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
983 tmp);
984 tmp &= ~(0xf << 20);
985 if (info->pex_type == MV_PEX_ROOT_COMPLEX)
986 tmp |= (0x4 << 20);
987 else
988 tmp |= (0x1 << 20);
989 reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
990 tmp);
991 DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
992 tmp);
993 }
994
995
996
997
998
999 DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
1000 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1001 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
1002 continue;
1003 if (info->pex_type == MV_PEX_END_POINT) {
1004 tmp =
1005 reg_read(PEX_DBG_CTRL_REG
1006 (MV_PEX_UNIT_TO_IF(pex_unit)));
1007 DEBUG_RD_REG(PEX_DBG_CTRL_REG
1008 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1009 tmp &= 0xfff6ffff;
1010 reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1011 tmp);
1012 DEBUG_WR_REG(PEX_DBG_CTRL_REG
1013 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1014 }
1015 }
1016
1017 if (info->serdes_m_phy_change) {
1018 MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
1019 u32 bus_speed;
1020 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
1021 line_cfg = get_line_cfg(line_num, info);
1022 if (line_cfg ==
1023 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
1024 continue;
1025 serdes_m_phy_change = info->serdes_m_phy_change;
1026 bus_speed = info->bus_speed & (1 << line_num);
1027 while (serdes_m_phy_change->type !=
1028 SERDES_UNIT_UNCONNECTED) {
1029 switch (serdes_m_phy_change->type) {
1030 case SERDES_UNIT_PEX:
1031 if (line_cfg != SERDES_UNIT_PEX)
1032 break;
1033 pex_unit = line_num >> 2;
1034 pex_line_num = line_num % 4;
1035 if (info->pex_mode[pex_unit] ==
1036 PEX_BUS_DISABLED)
1037 break;
1038 if ((info->pex_mode[pex_unit] ==
1039 PEX_BUS_MODE_X4) && pex_line_num)
1040 break;
1041
1042 if (bus_speed) {
1043 reg_write(PEX_PHY_ACCESS_REG
1044 (pex_unit),
1045 (pex_line_num << 24) |
1046 serdes_m_phy_change->val_hi_speed);
1047 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1048 (pex_unit),
1049 (pex_line_num <<
1050 24) |
1051 serdes_m_phy_change->val_hi_speed);
1052 } else {
1053 reg_write(PEX_PHY_ACCESS_REG
1054 (pex_unit),
1055 (pex_line_num << 24) |
1056 serdes_m_phy_change->val_low_speed);
1057 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1058 (pex_unit),
1059 (pex_line_num <<
1060 24) |
1061 serdes_m_phy_change->val_low_speed);
1062 }
1063 break;
1064 case SERDES_UNIT_SATA:
1065 if (line_cfg != SERDES_UNIT_SATA)
1066 break;
1067
1068
1069
1070
1071 sata_port = line_num & 1;
1072 if (bus_speed) {
1073 reg_write(SATA_BASE_REG
1074 (sata_port) |
1075 serdes_m_phy_change->reg_hi_speed,
1076 serdes_m_phy_change->val_hi_speed);
1077 DEBUG_WR_REG(SATA_BASE_REG
1078 (sata_port) |
1079 serdes_m_phy_change->reg_hi_speed,
1080 serdes_m_phy_change->val_hi_speed);
1081 } else {
1082 reg_write(SATA_BASE_REG
1083 (sata_port) |
1084 serdes_m_phy_change->reg_low_speed,
1085 serdes_m_phy_change->val_low_speed);
1086 DEBUG_WR_REG(SATA_BASE_REG
1087 (sata_port) |
1088 serdes_m_phy_change->reg_low_speed,
1089 serdes_m_phy_change->val_low_speed);
1090 }
1091 break;
1092 case SERDES_UNIT_SGMII0:
1093 case SERDES_UNIT_SGMII1:
1094 case SERDES_UNIT_SGMII2:
1095 case SERDES_UNIT_SGMII3:
1096 if (line_cfg == serdes_cfg[line_num]
1097 [SERDES_UNIT_SGMII0])
1098 sgmii_port = 0;
1099 else if (line_cfg ==
1100 serdes_cfg[line_num]
1101 [SERDES_UNIT_SGMII1])
1102 sgmii_port = 1;
1103 else if (line_cfg ==
1104 serdes_cfg[line_num]
1105 [SERDES_UNIT_SGMII2])
1106 sgmii_port = 2;
1107 else if (line_cfg ==
1108 serdes_cfg[line_num]
1109 [SERDES_UNIT_SGMII3])
1110 sgmii_port = 3;
1111 else
1112 break;
1113 if (bus_speed) {
1114 reg_write(MV_ETH_REGS_BASE
1115 (sgmii_port) |
1116 serdes_m_phy_change->reg_hi_speed,
1117 serdes_m_phy_change->val_hi_speed);
1118 DEBUG_WR_REG(MV_ETH_REGS_BASE
1119 (sgmii_port) |
1120 serdes_m_phy_change->reg_hi_speed,
1121 serdes_m_phy_change->val_hi_speed);
1122 } else {
1123 reg_write(MV_ETH_REGS_BASE
1124 (sgmii_port) |
1125 serdes_m_phy_change->reg_low_speed,
1126 serdes_m_phy_change->val_low_speed);
1127 DEBUG_WR_REG(MV_ETH_REGS_BASE
1128 (sgmii_port) |
1129 serdes_m_phy_change->reg_low_speed,
1130 serdes_m_phy_change->val_low_speed);
1131 }
1132 break;
1133 case SERDES_UNIT_QSGMII:
1134 if (line_cfg != SERDES_UNIT_QSGMII)
1135 break;
1136 if (bus_speed) {
1137 reg_write
1138 (serdes_m_phy_change->reg_hi_speed,
1139 serdes_m_phy_change->val_hi_speed);
1140 DEBUG_WR_REG
1141 (serdes_m_phy_change->reg_hi_speed,
1142 serdes_m_phy_change->val_hi_speed);
1143 } else {
1144 reg_write
1145 (serdes_m_phy_change->reg_low_speed,
1146 serdes_m_phy_change->val_low_speed);
1147 DEBUG_WR_REG
1148 (serdes_m_phy_change->reg_low_speed,
1149 serdes_m_phy_change->val_low_speed);
1150 }
1151 break;
1152 default:
1153 break;
1154 }
1155 serdes_m_phy_change++;
1156 }
1157 }
1158 }
1159
1160
1161 DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
1162 tmp = reg_read(SOC_CTRL_REG);
1163 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
1164 tmp &= ~(0x0F);
1165 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1166 reg_write(PEX_CAUSE_REG(pex_unit), 0);
1167 DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
1168 if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
1169 tmp |= (0x1 << pex_unit);
1170 }
1171 reg_write(SOC_CTRL_REG, tmp);
1172 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
1173
1174
1175 {
1176 u32 tmp_reg, tmp_pex_reg;
1177 u32 addr;
1178 u32 first_busno, next_busno;
1179 u32 max_link_width = 0;
1180 u32 neg_link_width = 0;
1181 pex_if_num = pex_max_if_get();
1182 mdelay(150);
1183 DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
1184 next_busno = 0;
1185 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1186 line_num = (pex_if <= 8) ? pex_if : 12;
1187 line_cfg = get_line_cfg(line_num, info);
1188 if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
1189 continue;
1190 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1191 DEBUG_INIT_FULL_S("step 17: PEX");
1192 DEBUG_INIT_FULL_D(pex_if, 1);
1193 DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
1194
1195 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1196 DEBUG_INIT_FULL_C("PEX disabled interface ",
1197 pex_if, 1);
1198 if (pex_if < 8)
1199 pex_if += 3;
1200 continue;
1201 }
1202 first_busno = next_busno;
1203 if ((info->pex_type == MV_PEX_END_POINT) &&
1204 (0 == pex_if)) {
1205 if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
1206 PEX_BUS_MODE_X4))
1207 pex_if += 3;
1208 continue;
1209 }
1210
1211 tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
1212 DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
1213 if ((tmp & 0x7f) == 0x7e) {
1214 next_busno++;
1215 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
1216 max_link_width = tmp;
1217 DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
1218 (pex_if)), tmp);
1219 max_link_width = ((max_link_width >> 4) & 0x3F);
1220 neg_link_width =
1221 reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
1222 DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
1223 neg_link_width);
1224 neg_link_width = ((neg_link_width >> 20) & 0x3F);
1225 if (max_link_width > neg_link_width) {
1226 tmp &= ~(0x3F << 4);
1227 tmp |= (neg_link_width << 4);
1228 reg_write(PEX_LINK_CAPABILITIES_REG
1229 (pex_if), tmp);
1230 DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
1231 (pex_if)), tmp);
1232 mdelay(1);
1233 DEBUG_INIT_S("PEX");
1234 DEBUG_INIT_D(pex_if, 1);
1235 DEBUG_INIT_C(": change width to X",
1236 neg_link_width, 1);
1237 }
1238 tmp_pex_reg =
1239 reg_read((PEX_CFG_DIRECT_ACCESS
1240 (pex_if,
1241 PEX_LINK_CAPABILITY_REG)));
1242 DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
1243 (pex_if,
1244 PEX_LINK_CAPABILITY_REG)),
1245 tmp_pex_reg);
1246 tmp_pex_reg &= (0xF);
1247 if (tmp_pex_reg == 0x2) {
1248 tmp_reg =
1249 (reg_read
1250 (PEX_CFG_DIRECT_ACCESS
1251 (pex_if,
1252 PEX_LINK_CTRL_STAT_REG)) &
1253 0xF0000) >> 16;
1254 DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
1255 (pex_if,
1256 PEX_LINK_CTRL_STAT_REG),
1257 tmp_pex_reg);
1258
1259 if (tmp_reg == 0x1) {
1260 pex_local_bus_num_set(pex_if,
1261 first_busno);
1262 pex_local_dev_num_set(pex_if,
1263 1);
1264
1265 DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
1266
1267 addr =
1268 pex_cfg_read(pex_if,
1269 first_busno, 0,
1270 0,
1271 0x34) & 0xFF;
1272 DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
1273 addr, 4);
1274 if (addr == 0xff) {
1275 DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
1276 pex_if, 1);
1277 continue;
1278 }
1279 while ((pex_cfg_read
1280 (pex_if, first_busno, 0,
1281 0,
1282 addr) & 0xFF) !=
1283 0x10) {
1284 addr =
1285 (pex_cfg_read
1286 (pex_if,
1287 first_busno, 0, 0,
1288 addr) & 0xFF00) >>
1289 8;
1290 }
1291 if ((pex_cfg_read
1292 (pex_if, first_busno, 0, 0,
1293 addr + 0xC) & 0xF) >=
1294 0x2) {
1295 tmp =
1296 reg_read
1297 (PEX_LINK_CTRL_STATUS2_REG
1298 (pex_if));
1299 DEBUG_RD_REG
1300 (PEX_LINK_CTRL_STATUS2_REG
1301 (pex_if), tmp);
1302 tmp &= ~(0x1 | 1 << 1);
1303 tmp |= (1 << 1);
1304 reg_write
1305 (PEX_LINK_CTRL_STATUS2_REG
1306 (pex_if), tmp);
1307 DEBUG_WR_REG
1308 (PEX_LINK_CTRL_STATUS2_REG
1309 (pex_if), tmp);
1310
1311 tmp =
1312 reg_read
1313 (PEX_CTRL_REG
1314 (pex_if));
1315 DEBUG_RD_REG
1316 (PEX_CTRL_REG
1317 (pex_if), tmp);
1318 tmp |= (1 << 10);
1319 reg_write(PEX_CTRL_REG
1320 (pex_if),
1321 tmp);
1322 DEBUG_WR_REG
1323 (PEX_CTRL_REG
1324 (pex_if), tmp);
1325 mdelay(10);
1326 DEBUG_INIT_FULL_S
1327 ("Gen2 client!\n");
1328 } else {
1329 DEBUG_INIT_FULL_S
1330 ("GEN1 client!\n");
1331 }
1332 }
1333 }
1334 } else {
1335 DEBUG_INIT_FULL_S("PEX");
1336 DEBUG_INIT_FULL_D(pex_if, 1);
1337 DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
1338 DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
1339 8);
1340 DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
1341 }
1342
1343 if ((pex_if < 8) &&
1344 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1345 pex_if += 3;
1346 }
1347 }
1348
1349
1350 {
1351 u32 devId;
1352 pex_if_num = pex_max_if_get();
1353 ctrl_mode = ctrl_model_get();
1354 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1355 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1356 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1357 if ((pex_if < 8) &&
1358 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1359 pex_if += 3;
1360 continue;
1361 }
1362
1363 devId = reg_read(PEX_CFG_DIRECT_ACCESS(
1364 pex_if, PEX_DEVICE_AND_VENDOR_ID));
1365 devId &= 0xFFFF;
1366 devId |= ((ctrl_mode << 16) & 0xffff0000);
1367 DEBUG_INIT_FULL_S("Update Device ID PEX");
1368 DEBUG_INIT_FULL_D(pex_if, 1);
1369 DEBUG_INIT_FULL_D(devId, 8);
1370 DEBUG_INIT_FULL_S("\n");
1371 reg_write(PEX_CFG_DIRECT_ACCESS
1372 (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
1373 if ((pex_if < 8) &&
1374 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1375 pex_if += 3;
1376 }
1377 DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
1378 DEBUG_INIT_FULL_D(ctrl_mode, 4);
1379 DEBUG_INIT_FULL_S("0\n");
1380 }
1381 tmp = reg_read(PEX_DBG_STATUS_REG(0));
1382 DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
1383
1384 DEBUG_INIT_S(ENDED_OK);
1385 return MV_OK;
1386}
1387
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1413
1414u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
1415{
1416 u32 pex_data = 0;
1417 u32 local_dev, local_bus;
1418 u32 val;
1419
1420 if (pex_if >= MV_PEX_MAX_IF)
1421 return 0xFFFFFFFF;
1422
1423 if (dev >= MAX_PEX_DEVICES) {
1424 DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
1425 1);
1426 return 0xFFFFFFFF;
1427 }
1428
1429 if (func >= MAX_PEX_FUNCS) {
1430 DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
1431 1);
1432 return 0xFFFFFFFF;
1433 }
1434
1435 if (bus >= MAX_PEX_BUSSES) {
1436 DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
1437 return MV_ERROR;
1438 }
1439 val = reg_read(PEX_STATUS_REG(pex_if));
1440
1441 local_dev =
1442 ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
1443 local_bus =
1444 ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
1445
1446
1447 if ((dev != local_dev) || (bus != local_bus)) {
1448 pex_data = reg_read(PEX_STATUS_REG(pex_if));
1449
1450 if ((pex_data & PXSR_DL_DOWN))
1451 return MV_ERROR;
1452 }
1453
1454
1455
1456
1457
1458
1459 if (bus == local_bus) {
1460 if (local_dev == 0) {
1461
1462
1463
1464
1465 if ((dev != 1) && (dev != local_dev))
1466 return MV_ERROR;
1467 } else {
1468
1469
1470
1471
1472 if ((dev != 0) && (dev != local_dev))
1473 return MV_ERROR;
1474 }
1475 }
1476
1477
1478 pex_data = (bus << PXCAR_BUS_NUM_OFFS);
1479 pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
1480 pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
1481 pex_data |= (offs & PXCAR_REG_NUM_MASK);
1482
1483 pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
1484 PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
1485
1486 pex_data |= PXCAR_CONFIG_EN;
1487
1488
1489 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
1490
1491
1492
1493
1494
1495 if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
1496 return MV_ERROR;
1497
1498
1499 reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
1500 PXSAC_MABORT);
1501
1502 pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
1503
1504 DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
1505
1506 return pex_data;
1507}
1508
1509
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1528
1529int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
1530{
1531 u32 val;
1532
1533 if (bus_num >= MAX_PEX_BUSSES) {
1534 DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
1535 bus_num, 4);
1536 return MV_ERROR;
1537 }
1538
1539 val = reg_read(PEX_STATUS_REG(pex_if));
1540 val &= ~PXSR_PEX_BUS_NUM_MASK;
1541 val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
1542 reg_write(PEX_STATUS_REG(pex_if), val);
1543
1544 return MV_OK;
1545}
1546
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1565
1566
1567int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
1568{
1569 u32 val;
1570
1571 if (pex_if >= MV_PEX_MAX_IF)
1572 return MV_BAD_PARAM;
1573
1574 val = reg_read(PEX_STATUS_REG(pex_if));
1575 val &= ~PXSR_PEX_DEV_NUM_MASK;
1576 val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
1577 reg_write(PEX_STATUS_REG(pex_if), val);
1578
1579 return MV_OK;
1580}
1581
