1/* 2 * mcf5282.h -- Definitions for Motorola Coldfire 5282 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/****************************************************************************/ 8#ifndef m5282_h 9#define m5282_h 10 11/********************************************************************* 12* PLL Clock Module 13*********************************************************************/ 14/* Bit definitions and macros for PLL_SYNCR */ 15#define PLL_SYNCR_LOLRE (0x8000) 16#define PLL_SYNCR_MFD2 (0x4000) 17#define PLL_SYNCR_MFD1 (0x2000) 18#define PLL_SYNCR_MFD0 (0x1000) 19#define PLL_SYNCR_LOCRE (0x0800) 20#define PLL_SYNCR_RFC2 (0x0400) 21#define PLL_SYNCR_RFC1 (0x0200) 22#define PLL_SYNCR_RFC0 (0x0100) 23#define PLL_SYNCR_LOCEN (0x0080) 24#define PLL_SYNCR_DISCLK (0x0040) 25#define PLL_SYNCR_FWKUP (0x0020) 26#define PLL_SYNCR_STPMD1 (0x0008) 27#define PLL_SYNCR_STPMD0 (0x0004) 28 29/* Bit definitions and macros for PLL_SYNSR */ 30#define PLL_SYNSR_MODE (0x0080) 31#define PLL_SYNSR_PLLSEL (0x0040) 32#define PLL_SYNSR_PLLREF (0x0020) 33#define PLL_SYNSR_LOCKS (0x0010) 34#define PLL_SYNSR_LOCK (0x0008) 35#define PLL_SYNSR_LOCS (0x0004) 36 37/********************************************************************* 38* Interrupt Controller (INTC) 39*********************************************************************/ 40#define INT0_LO_RSVD0 (0) 41#define INT0_LO_EPORT1 (1) 42#define INT0_LO_EPORT2 (2) 43#define INT0_LO_EPORT3 (3) 44#define INT0_LO_EPORT4 (4) 45#define INT0_LO_EPORT5 (5) 46#define INT0_LO_EPORT6 (6) 47#define INT0_LO_EPORT7 (7) 48#define INT0_LO_SCM_SWT1 (8) 49#define INT0_LO_DMA_00 (9) 50#define INT0_LO_DMA_01 (10) 51#define INT0_LO_DMA_02 (11) 52#define INT0_LO_DMA_03 (12) 53#define INT0_LO_UART0 (13) 54#define INT0_LO_UART1 (14) 55#define INT0_LO_UART2 (15) 56#define INT0_LO_RSVD1 (16) 57#define INT0_LO_I2C (17) 58#define INT0_LO_QSPI (18) 59#define INT0_LO_DTMR0 (19) 60#define INT0_LO_DTMR1 (20) 61#define INT0_LO_DTMR2 (21) 62#define INT0_LO_DTMR3 (22) 63#define INT0_LO_FEC_TXF (23) 64#define INT0_LO_FEC_TXB (24) 65#define INT0_LO_FEC_UN (25) 66#define INT0_LO_FEC_RL (26) 67#define INT0_LO_FEC_RXF (27) 68#define INT0_LO_FEC_RXB (28) 69#define INT0_LO_FEC_MII (29) 70#define INT0_LO_FEC_LC (30) 71#define INT0_LO_FEC_HBERR (31) 72#define INT0_HI_FEC_GRA (32) 73#define INT0_HI_FEC_EBERR (33) 74#define INT0_HI_FEC_BABT (34) 75#define INT0_HI_FEC_BABR (35) 76#define INT0_HI_PMM_LVDF (36) 77#define INT0_HI_QADC_CF1 (37) 78#define INT0_HI_QADC_CF2 (38) 79#define INT0_HI_QADC_PF1 (39) 80#define INT0_HI_QADC_PF2 (40) 81#define INT0_HI_GPTA_TOF (41) 82#define INT0_HI_GPTA_PAIF (42) 83#define INT0_HI_GPTA_PAOVF (43) 84#define INT0_HI_GPTA_C0F (44) 85#define INT0_HI_GPTA_C1F (45) 86#define INT0_HI_GPTA_C2F (46) 87#define INT0_HI_GPTA_C3F (47) 88#define INT0_HI_GPTB_TOF (48) 89#define INT0_HI_GPTB_PAIF (49) 90#define INT0_HI_GPTB_PAOVF (50) 91#define INT0_HI_GPTB_C0F (51) 92#define INT0_HI_GPTB_C1F (52) 93#define INT0_HI_GPTB_C2F (53) 94#define INT0_HI_GPTB_C3F (54) 95#define INT0_HI_PIT0 (55) 96#define INT0_HI_PIT1 (56) 97#define INT0_HI_PIT2 (57) 98#define INT0_HI_PIT3 (58) 99#define INT0_HI_CFM_CBEIF (59) 100#define INT0_HI_CFM_CCIF (60) 101#define INT0_HI_CFM_PVIF (61) 102#define INT0_HI_CFM_AEIF (62) 103 104/* 105 * Size of internal RAM 106 */ 107 108#define INT_RAM_SIZE 65536 109 110/* General Purpose I/O Module GPIO */ 111 112#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) 113#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) 114#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) 115#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) 116#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) 117#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) 118#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) 119#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) 120#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) 121#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) 122#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) 123#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) 124#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) 125#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) 126#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) 127#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) 128#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) 129#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) 130 131#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) 132#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) 133#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) 134#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) 135#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) 136#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) 137#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) 138#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) 139#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) 140#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) 141#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) 142#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) 143#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) 144#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) 145#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) 146#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) 147#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) 148#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) 149 150#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) 151#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) 152#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) 153#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) 154#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) 155#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) 156#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) 157#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) 158#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) 159#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) 160#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) 161#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) 162#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) 163#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) 164#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) 165#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) 166#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) 167#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) 168 169#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) 170#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) 171#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) 172#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) 173#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) 174#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) 175#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) 176#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) 177#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) 178#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) 179#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) 180#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) 181#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) 182#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) 183#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) 184#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) 185#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) 186#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) 187 188#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) 189#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) 190#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) 191#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) 192#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) 193#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) 194#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) 195#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) 196#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) 197#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) 198#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) 199#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) 200#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) 201#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) 202#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) 203#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) 204#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) 205#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) 206 207#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) 208#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) 209#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) 210#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) 211#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) 212#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) 213#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) 214#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) 215#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) 216#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) 217#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) 218 219/* Bit level definitions and macros */ 220#define MCFGPIO_PORT7 (0x80) 221#define MCFGPIO_PORT6 (0x40) 222#define MCFGPIO_PORT5 (0x20) 223#define MCFGPIO_PORT4 (0x10) 224#define MCFGPIO_PORT3 (0x08) 225#define MCFGPIO_PORT2 (0x04) 226#define MCFGPIO_PORT1 (0x02) 227#define MCFGPIO_PORT0 (0x01) 228#define MCFGPIO_PORT(x) (0x01<<x) 229 230#define MCFGPIO_DDR7 (0x80) 231#define MCFGPIO_DDR6 (0x40) 232#define MCFGPIO_DDR5 (0x20) 233#define MCFGPIO_DDR4 (0x10) 234#define MCFGPIO_DDR3 (0x08) 235#define MCFGPIO_DDR2 (0x04) 236#define MCFGPIO_DDR1 (0x02) 237#define MCFGPIO_DDR0 (0x01) 238#define MCFGPIO_DDR(x) (0x01<<x) 239 240#define MCFGPIO_Px7 (0x80) 241#define MCFGPIO_Px6 (0x40) 242#define MCFGPIO_Px5 (0x20) 243#define MCFGPIO_Px4 (0x10) 244#define MCFGPIO_Px3 (0x08) 245#define MCFGPIO_Px2 (0x04) 246#define MCFGPIO_Px1 (0x02) 247#define MCFGPIO_Px0 (0x01) 248#define MCFGPIO_Px(x) (0x01<<x) 249 250#define MCFGPIO_PBCDPAR_PBPA (0x80) 251#define MCFGPIO_PBCDPAR_PCDPA (0x40) 252 253#define MCFGPIO_PEPAR_PEPA7 (0x4000) 254#define MCFGPIO_PEPAR_PEPA6 (0x1000) 255#define MCFGPIO_PEPAR_PEPA5 (0x0400) 256#define MCFGPIO_PEPAR_PEPA4 (0x0100) 257#define MCFGPIO_PEPAR_PEPA3 (0x0040) 258#define MCFGPIO_PEPAR_PEPA2 (0x0010) 259#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) 260#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3)) 261 262#define MCFGPIO_PFPAR_PFPA7 (0x80) 263#define MCFGPIO_PFPAR_PFPA6 (0x40) 264#define MCFGPIO_PFPAR_PFPA5 (0x20) 265 266#define MCFGPIO_PJPAR_PJPA7 (0x80) 267#define MCFGPIO_PJPAR_PJPA6 (0x40) 268#define MCFGPIO_PJPAR_PJPA5 (0x20) 269#define MCFGPIO_PJPAR_PJPA4 (0x10) 270#define MCFGPIO_PJPAR_PJPA3 (0x08) 271#define MCFGPIO_PJPAR_PJPA2 (0x04) 272#define MCFGPIO_PJPAR_PJPA1 (0x02) 273#define MCFGPIO_PJPAR_PJPA0 (0x01) 274#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x) 275 276#define MCFGPIO_PSDPAR_PSDPA (0x80) 277 278#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) 279#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) 280#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) 281#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) 282#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) 283#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3)) 284 285#define MCFGPIO_PEHLPAR_PEHPA (0x80) 286#define MCFGPIO_PEHLPAR_PELPA (0x40) 287 288#define MCFGPIO_PQSPAR_PQSPA6 (0x40) 289#define MCFGPIO_PQSPAR_PQSPA5 (0x20) 290#define MCFGPIO_PQSPAR_PQSPA4 (0x10) 291#define MCFGPIO_PQSPAR_PQSPA3 (0x08) 292#define MCFGPIO_PQSPAR_PQSPA2 (0x04) 293#define MCFGPIO_PQSPAR_PQSPA1 (0x02) 294#define MCFGPIO_PQSPAR_PQSPA0 (0x01) 295#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x) 296 297#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) 298#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) 299#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) 300#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) 301 302#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) 303#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) 304#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) 305#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) 306 307#define MCFGPIO_PUAPAR_PUAPA3 (0x08) 308#define MCFGPIO_PUAPAR_PUAPA2 (0x04) 309#define MCFGPIO_PUAPAR_PUAPA1 (0x02) 310#define MCFGPIO_PUAPAR_PUAPA0 (0x01) 311 312/* System Conrol Module SCM */ 313 314#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) 315#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) 316#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) 317#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) 318#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) 319 320#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) 321#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) 322#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) 323#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) 324#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) 325#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) 326#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) 327#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) 328#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) 329#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) 330#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) 331#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) 332#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) 333 334#define MCFSCM_CRSR_EXT (0x80) 335#define MCFSCM_CRSR_CWDR (0x20) 336#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000) 337#define MCFSCM_RAMBAR_BDE (0x00000200) 338 339/* Reset Controller Module RCM */ 340 341#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) 342#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) 343 344#define MCFRESET_RCR_SOFTRST (0x80) 345#define MCFRESET_RCR_FRCRSTOUT (0x40) 346#define MCFRESET_RCR_LVDF (0x10) 347#define MCFRESET_RCR_LVDIE (0x08) 348#define MCFRESET_RCR_LVDRE (0x04) 349#define MCFRESET_RCR_LVDE (0x01) 350 351#define MCFRESET_RSR_LVD (0x40) 352#define MCFRESET_RSR_SOFT (0x20) 353#define MCFRESET_RSR_WDR (0x10) 354#define MCFRESET_RSR_POR (0x08) 355#define MCFRESET_RSR_EXT (0x04) 356#define MCFRESET_RSR_LOC (0x02) 357#define MCFRESET_RSR_LOL (0x01) 358#define MCFRESET_RSR_ALL (0x7F) 359#define MCFRESET_RCR_SOFTRST (0x80) 360#define MCFRESET_RCR_FRCRSTOUT (0x40) 361 362/* Chip Configuration Module CCM */ 363 364#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) 365#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) 366#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) 367 368/* Bit level definitions and macros */ 369#define MCFCCM_CCR_LOAD (0x8000) 370#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) 371#define MCFCCM_CCR_SZEN (0x0040) 372#define MCFCCM_CCR_PSTEN (0x0020) 373#define MCFCCM_CCR_BME (0x0008) 374#define MCFCCM_CCR_BMT(x) (((x)&0x0007)) 375 376#define MCFCCM_CIR_PIN_MASK (0xFF00) 377#define MCFCCM_CIR_PRN_MASK (0x00FF) 378 379/* Clock Module */ 380 381#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) 382#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) 383 384#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) 385#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) 386#define MCFCLOCK_SYNSR_LOCK 0x08 387 388#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) 389#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) 390#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) 391#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) 392#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) 393 394#define MCFSDRAMC_DCR_NAM (0x2000) 395#define MCFSDRAMC_DCR_COC (0x1000) 396#define MCFSDRAMC_DCR_IS (0x0800) 397#define MCFSDRAMC_DCR_RTIM_3 (0x0000) 398#define MCFSDRAMC_DCR_RTIM_6 (0x0200) 399#define MCFSDRAMC_DCR_RTIM_9 (0x0400) 400#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF) 401 402#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) 403#define MCFSDRAMC_DACR_RE (0x00008000) 404#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12) 405#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8) 406#define MCFSDRAMC_DACR_PS_32 (0x00000000) 407#define MCFSDRAMC_DACR_PS_16 (0x00000020) 408#define MCFSDRAMC_DACR_PS_8 (0x00000010) 409#define MCFSDRAMC_DACR_IP (0x00000008) 410#define MCFSDRAMC_DACR_IMRS (0x00000040) 411 412#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000) 413#define MCFSDRAMC_DMR_WP (0x00000100) 414#define MCFSDRAMC_DMR_CI (0x00000040) 415#define MCFSDRAMC_DMR_AM (0x00000020) 416#define MCFSDRAMC_DMR_SC (0x00000010) 417#define MCFSDRAMC_DMR_SD (0x00000008) 418#define MCFSDRAMC_DMR_UC (0x00000004) 419#define MCFSDRAMC_DMR_UD (0x00000002) 420#define MCFSDRAMC_DMR_V (0x00000001) 421 422#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) 423#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) 424#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) 425#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) 426 427/********************************************************************* 428* General Purpose Timer (GPT) Module 429*********************************************************************/ 430 431#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) 432#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) 433#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) 434#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) 435#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) 436#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) 437#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) 438#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) 439#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) 440#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) 441#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) 442#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) 443#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) 444#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) 445#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) 446#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) 447#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) 448#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) 449#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) 450#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) 451#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) 452#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) 453 454#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) 455#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) 456#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) 457#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) 458#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) 459#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) 460#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) 461#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) 462#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) 463#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) 464#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) 465#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) 466#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) 467#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) 468#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) 469#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) 470#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) 471#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) 472#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) 473#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) 474#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) 475#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) 476 477/* Bit level definitions and macros */ 478#define MCFGPT_GPTIOS_IOS3 (0x08) 479#define MCFGPT_GPTIOS_IOS2 (0x04) 480#define MCFGPT_GPTIOS_IOS1 (0x02) 481#define MCFGPT_GPTIOS_IOS0 (0x01) 482 483#define MCFGPT_GPTCFORC_FOC3 (0x08) 484#define MCFGPT_GPTCFORC_FOC2 (0x04) 485#define MCFGPT_GPTCFORC_FOC1 (0x02) 486#define MCFGPT_GPTCFORC_FOC0 (0x01) 487 488#define MCFGPT_GPTOC3M_OC3M3 (0x08) 489#define MCFGPT_GPTOC3M_OC3M2 (0x04) 490#define MCFGPT_GPTOC3M_OC3M1 (0x02) 491#define MCFGPT_GPTOC3M_OC3M0 (0x01) 492 493#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04)) 494 495#define MCFGPT_GPTSCR1_GPTEN (0x80) 496#define MCFGPT_GPTSCR1_TFFCA (0x10) 497 498#define MCFGPT_GPTTOV3 (0x08) 499#define MCFGPT_GPTTOV2 (0x04) 500#define MCFGPT_GPTTOV1 (0x02) 501#define MCFGPT_GPTTOV0 (0x01) 502 503#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) 504#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) 505#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) 506#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03)) 507 508#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) 509#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) 510#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) 511#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03)) 512 513#define MCFGPT_GPTIE_C3I (0x08) 514#define MCFGPT_GPTIE_C2I (0x04) 515#define MCFGPT_GPTIE_C1I (0x02) 516#define MCFGPT_GPTIE_C0I (0x01) 517 518#define MCFGPT_GPTSCR2_TOI (0x80) 519#define MCFGPT_GPTSCR2_PUPT (0x20) 520#define MCFGPT_GPTSCR2_RDPT (0x10) 521#define MCFGPT_GPTSCR2_TCRE (0x08) 522#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07)) 523 524#define MCFGPT_GPTFLG1_C3F (0x08) 525#define MCFGPT_GPTFLG1_C2F (0x04) 526#define MCFGPT_GPTFLG1_C1F (0x02) 527#define MCFGPT_GPTFLG1_C0F (0x01) 528 529#define MCFGPT_GPTFLG2_TOF (0x80) 530#define MCFGPT_GPTFLG2_C3F (0x08) 531#define MCFGPT_GPTFLG2_C2F (0x04) 532#define MCFGPT_GPTFLG2_C1F (0x02) 533#define MCFGPT_GPTFLG2_C0F (0x01) 534 535#define MCFGPT_GPTPACTL_PAE (0x40) 536#define MCFGPT_GPTPACTL_PAMOD (0x20) 537#define MCFGPT_GPTPACTL_PEDGE (0x10) 538#define MCFGPT_GPTPACTL_CLK_PACLK (0x04) 539#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08) 540#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C) 541#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) 542#define MCFGPT_GPTPACTL_PAOVI (0x02) 543#define MCFGPT_GPTPACTL_PAI (0x01) 544 545#define MCFGPT_GPTPAFLG_PAOVF (0x02) 546#define MCFGPT_GPTPAFLG_PAIF (0x01) 547 548#define MCFGPT_GPTPORT_PORTT3 (0x08) 549#define MCFGPT_GPTPORT_PORTT2 (0x04) 550#define MCFGPT_GPTPORT_PORTT1 (0x02) 551#define MCFGPT_GPTPORT_PORTT0 (0x01) 552 553#define MCFGPT_GPTDDR_DDRT3 (0x08) 554#define MCFGPT_GPTDDR_DDRT2 (0x04) 555#define MCFGPT_GPTDDR_DDRT1 (0x02) 556#define MCFGPT_GPTDDR_DDRT0 (0x01) 557 558/* Coldfire Flash Module CFM */ 559 560#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) 561#define MCFCFM_MCR_LOCK (0x0400) 562#define MCFCFM_MCR_PVIE (0x0200) 563#define MCFCFM_MCR_AEIE (0x0100) 564#define MCFCFM_MCR_CBEIE (0x0080) 565#define MCFCFM_MCR_CCIE (0x0040) 566#define MCFCFM_MCR_KEYACC (0x0020) 567 568#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) 569 570#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) 571#define MCFCFM_SEC_KEYEN (0x80000000) 572#define MCFCFM_SEC_SECSTAT (0x40000000) 573 574#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) 575#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) 576#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) 577#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) 578#define MCFCFM_USTAT_CBEIF 0x80 579#define MCFCFM_USTAT_CCIF 0x40 580#define MCFCFM_USTAT_PVIOL 0x20 581#define MCFCFM_USTAT_ACCERR 0x10 582#define MCFCFM_USTAT_BLANK 0x04 583 584#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) 585#define MCFCFM_CMD_ERSVER 0x05 586#define MCFCFM_CMD_PGERSVER 0x06 587#define MCFCFM_CMD_PGM 0x20 588#define MCFCFM_CMD_PGERS 0x40 589#define MCFCFM_CMD_MASERS 0x41 590 591/****************************************************************************/ 592#endif /* m5282_h */ 593