LXR uboot/arch/mips/mach-au1x00/au1x00

   1/* Only eth0 supported for now
   2 *
   3 * (C) Copyright 2003
   4 * Thomas.Lange@corelatus.se
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8#include <config.h>
   9
  10#if defined(CONFIG_SYS_DISCOVER_PHY)
  11#error "PHY not supported yet"
  12/* We just assume that we are running 100FD for now */
  13/* We all use switches, right? ;-) */
  14#endif
  15
  16/* I assume ethernet behaves like au1000 */
  17
  18#ifdef CONFIG_SOC_AU1000
  19/* Base address differ between cpu:s */
  20#define ETH0_BASE AU1000_ETH0_BASE
  21#define MAC0_ENABLE AU1000_MAC0_ENABLE
  22#else
  23#ifdef CONFIG_SOC_AU1100
  24#define ETH0_BASE AU1100_ETH0_BASE
  25#define MAC0_ENABLE AU1100_MAC0_ENABLE
  26#else
  27#ifdef CONFIG_SOC_AU1500
  28#define ETH0_BASE AU1500_ETH0_BASE
  29#define MAC0_ENABLE AU1500_MAC0_ENABLE
  30#else
  31#ifdef CONFIG_SOC_AU1550
  32#define ETH0_BASE AU1550_ETH0_BASE
  33#define MAC0_ENABLE AU1550_MAC0_ENABLE
  34#else
  35#error "No valid cpu set"
  36#endif
  37#endif
  38#endif
  39#endif
  40
  41#include <common.h>
  42#include <malloc.h>
  43#include <net.h>
  44#include <command.h>
  45#include <asm/io.h>
  46#include <mach/au1x00.h>
  47
  48#if defined(CONFIG_CMD_MII)
  49#include <miiphy.h>
  50#endif
  51
  52/* Ethernet Transmit and Receive Buffers */
  53#define DBUF_LENGTH  1520
  54#define PKT_MAXBUF_SIZE         1518
  55
  56static char txbuf[DBUF_LENGTH];
  57
  58static int next_tx;
  59static int next_rx;
  60
  61/* 4 rx and 4 tx fifos */
  62#define NO_OF_FIFOS 4
  63
  64typedef struct{
  65        u32 status;
  66        u32 addr;
  67        u32 len; /* Only used for tx */
  68        u32 not_used;
  69} mac_fifo_t;
  70
  71mac_fifo_t mac_fifo[NO_OF_FIFOS];
  72
  73#define MAX_WAIT 1000
  74
  75#if defined(CONFIG_CMD_MII)
  76int  au1x00_miiphy_read(const char *devname, unsigned char addr,
  77                unsigned char reg, unsigned short * value)
  78{
  79        volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
  80        volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
  81        u32 mii_control;
  82        unsigned int timedout = 20;
  83
  84        while (*mii_control_reg & MAC_MII_BUSY) {
  85                udelay(1000);
  86                if (--timedout == 0) {
  87                        printf("au1x00_eth: miiphy_read busy timeout!!\n");
  88                        return -1;
  89                }
  90        }
  91
  92        mii_control = MAC_SET_MII_SELECT_REG(reg) |
  93                MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
  94
  95        *mii_control_reg = mii_control;
  96
  97        timedout = 20;
  98        while (*mii_control_reg & MAC_MII_BUSY) {
  99                udelay(1000);
 100                if (--timedout == 0) {
 101                        printf("au1x00_eth: miiphy_read busy timeout!!\n");
 102                        return -1;
 103                }
 104        }
 105        *value = *mii_data_reg;
 106        return 0;
 107}
 108
 109int  au1x00_miiphy_write(const char *devname, unsigned char addr,
 110                unsigned char reg, unsigned short value)
 111{
 112        volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
 113        volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
 114        u32 mii_control;
 115        unsigned int timedout = 20;
 116
 117        while (*mii_control_reg & MAC_MII_BUSY) {
 118                udelay(1000);
 119                if (--timedout == 0) {
 120                        printf("au1x00_eth: miiphy_write busy timeout!!\n");
 121                        return -1;
 122                }
 123        }
 124
 125        mii_control = MAC_SET_MII_SELECT_REG(reg) |
 126                MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
 127
 128        *mii_data_reg = value;
 129        *mii_control_reg = mii_control;
 130        return 0;
 131}
 132#endif
 133
 134static int au1x00_send(struct eth_device *dev, void *packet, int length)
 135{
 136        volatile mac_fifo_t *fifo_tx =
 137                (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 138        int i;
 139        int res;
 140
 141        /* tx fifo should always be idle */
 142        fifo_tx[next_tx].len = length;
 143        fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
 144        au_sync();
 145
 146        udelay(1);
 147        i=0;
 148        while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
 149                if(i>MAX_WAIT){
 150                        printf("TX timeout\n");
 151                        break;
 152                }
 153                udelay(1);
 154                i++;
 155        }
 156
 157        /* Clear done bit */
 158        fifo_tx[next_tx].addr = 0;
 159        fifo_tx[next_tx].len = 0;
 160        au_sync();
 161
 162        res = fifo_tx[next_tx].status;
 163
 164        next_tx++;
 165        if(next_tx>=NO_OF_FIFOS){
 166                next_tx=0;
 167        }
 168        return(res);
 169}
 170
 171static int au1x00_recv(struct eth_device* dev){
 172        volatile mac_fifo_t *fifo_rx =
 173                (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 174
 175        int length;
 176        u32 status;
 177
 178        for(;;){
 179                if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
 180                        /* Nothing has been received */
 181                        return(-1);
 182                }
 183
 184                status = fifo_rx[next_rx].status;
 185
 186                length = status&0x3FFF;
 187
 188                if(status&RX_ERROR){
 189                        printf("Rx error 0x%x\n", status);
 190                } else {
 191                        /* Pass the packet up to the protocol layers. */
 192                        net_process_received_packet(net_rx_packets[next_rx],
 193                                                    length - 4);
 194                }
 195
 196                fifo_rx[next_rx].addr =
 197                        (virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
 198
 199                next_rx++;
 200                if(next_rx>=NO_OF_FIFOS){
 201                        next_rx=0;
 202                }
 203        } /* for */
 204
 205        return(0); /* Does anyone use this? */
 206}
 207
 208static int au1x00_init(struct eth_device* dev, bd_t * bd){
 209
 210        volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 211        volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
 212        volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
 213        volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
 214        volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
 215        volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
 216        volatile mac_fifo_t *fifo_tx =
 217                (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 218        volatile mac_fifo_t *fifo_rx =
 219                (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 220        int i;
 221
 222        next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
 223        next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
 224
 225        /* We have to enable clocks before releasing reset */
 226        *macen = MAC_EN_CLOCK_ENABLE;
 227        udelay(10);
 228
 229        /* Enable MAC0 */
 230        /* We have to release reset before accessing registers */
 231        *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
 232                MAC_EN_RESET1|MAC_EN_RESET2;
 233        udelay(10);
 234
 235        for(i=0;i<NO_OF_FIFOS;i++){
 236                fifo_tx[i].len = 0;
 237                fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
 238                fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
 239                        RX_DMA_ENABLE;
 240        }
 241
 242        /* Put mac addr in little endian */
 243#define ea eth_get_ethaddr()
 244        *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
 245        *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
 246                (ea[1] <<  8) | (ea[0]      ) ;
 247#undef ea
 248        *mac_mcast_low = 0;
 249        *mac_mcast_high = 0;
 250
 251        /* Make sure the MAC buffer is in the correct endian mode */
 252#ifdef __LITTLE_ENDIAN
 253        *mac_ctrl = MAC_FULL_DUPLEX;
 254        udelay(1);
 255        *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 256#else
 257        *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
 258        udelay(1);
 259        *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 260#endif
 261
 262        return(1);
 263}
 264
 265static void au1x00_halt(struct eth_device* dev){
 266        volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 267
 268        /* Put MAC0 in reset */
 269        *macen = 0;
 270}
 271
 272int au1x00_enet_initialize(bd_t *bis){
 273        struct eth_device* dev;
 274
 275        if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
 276                puts ("malloc failed\n");
 277                return -1;
 278        }
 279
 280        memset(dev, 0, sizeof *dev);
 281
 282        strcpy(dev->name, "Au1X00 ethernet");
 283        dev->iobase = 0;
 284        dev->priv   = 0;
 285        dev->init   = au1x00_init;
 286        dev->halt   = au1x00_halt;
 287        dev->send   = au1x00_send;
 288        dev->recv   = au1x00_recv;
 289
 290        eth_register(dev);
 291
 292#if defined(CONFIG_CMD_MII)
 293        miiphy_register(dev->name,
 294                au1x00_miiphy_read, au1x00_miiphy_write);
 295#endif
 296
 297        return 1;
 298}
 299
 300int cpu_eth_init(bd_t *bis)
 301{
 302        au1x00_enet_initialize(bis);
 303        return 0;
 304}
 305